An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ###########################
E2V TECHNOLOGIES : e2v first to introduce 12bit 1.5 GSPS analogue to digital converter with both direct RF sampling in L-band and low input voltage range News Items
e2v first to introduce 12bit 1.5 GSPS analogue to digital converter with both direct RF sampling in L-band and low input voltage range date added : September 12, 2011
Building on the performance of its true single core high bandwidth family of ADCs with direct RF sampling, e2v announces the launch of
EV12AS200, a 12-bit 1.5 GSPS analogue to digital converter. #########################################
The new ADC combines the benefits of direct RF sampling up to L band, ##################################################
calibration free stable performance versus temperature and a wider choice of ADC input driving options, thanks to the lowest input voltage range on the market for 12bit GSPS ADCs.
This device enables further innovation in high verticality oscilloscopes, spectrum analysers, high dynamic range point-to-point microwave data links, electronic warfare systems and data acquisition COTS boards.
The EV12AS200 features a full power input bandwidth of 2.3GHz with a roll-off pattern optimised for operation in the L-band area. It also features the lowest input voltage range in the 12bit GSPS class with only 500mVp-p, without sacrificing performance in direct RF sampling. This delivers a significant reduction in distortion effects induced by high voltage swings at high frequencies in any amplifiers used prior to the ADC, such as variable gain amplifiers used for signal zooming purposes.
The low input voltage range of EV12AS200 is also a very convenient feature to build high verticality oscilloscopes with multiple amplification stages prior to the ADC while maintaining a very low level of distortion in the amplifiers.
EV12AS200 is also the only 12bit ADC operating at up to 1.5 GSPS without the use of any form of internal interleaving. ###############################################################################
! (ot awtora postinga) ###############
This is key for the EV12AS200 to achieve both a calibration-free stable dynamic performance versus temperature, and nominal dynamic performance that is available immediately at power-up as soon as the supply voltage has stabilised, without the need to wait for multi-second silicon warm-up and calibration.
Other noticeable benefits of EV12AS200 include a low latency of fewer than 5 clock cycles, which is convenient for real time systems, guaranteed no-missing codes at 1.5GSPS, important for high verticality oscilloscopes, an analogue and clock input impedance of 100 Ohms that is stable versus frequency and temperature, and fine adjustments of input gain and offset as well as clock skew, which facilitates interleaving of multiple converters to achieve even higher sample rates.
“This new ADC brings all the recognised benefits of e2v data converters familiar at 8 and 10 bit into the 12 bit GSPS class and enables further innovation in both direct RF sampling with stable performance at all temperatures and input driving flexibility. It also opens new possibilities for high resolution time domain applications such as high verticality oscilloscopes” said Nicolas Chantier, Product Marketing for e2v’s Broadband data conversion product line.
EV12AS200 is offered in a small footprint FpBGA 196 package with the choice of commercial temperature grade (0°C to +90°C) or industrial temperature grade (-40°C to +110°C).
Datasheet, samples and quotations are now available from e2v and from e2v’s authorised distributors around the world.
e2v is a leading global provider of specialist technology for high performance systems and equipment; delivering solutions, sub-systems and components for specialist applications within medical & science, aerospace & defence, and commercial & industrial markets.
e2v is headquartered in the UK, employs approximately 1500 people, has design and production facilities across Europe and North America, and has a global network of sales and technical support offices. For the year ended 31 March 2011, e2v reported sales of £229m and is listed on the London Stock Exchange. For more information visit e2v.com.
With over 20 years experience in the design and manufacture of advanced semiconductor components, e2v provides broadband data converters with high resolution (from 6 to 12 bits), high sampling rates (from 250 Msps to 5Gsps) and wide bandwidth (up to 5GHz)
e2v's family of 8, 10 and 12-bit A/D converters has grown to include sampling rates from 500 Msps to 5Gsps; all without the need for added off-chip external interleaving techniques.
e2v ADC's provide reveiver designers with market leading high linearity, ENOB and dynamic range coupled with analog bandwidths from 1GHz to over 3GHz for true high IF sampling.
Excellent noise and linearity up to and above fIN = 2.7 GHz Configurable to either 3.6 GSPS interleaved or 1800 MSPS dual ADC New DESCLKIQ Mode for high bandwidth, high sampling rate apps Pin-compatible with ADC1xD1x00, ADC12Dx00RF AutoSync feature for multi-chip synchronization Internally terminated, buffered, differential analog inputs Interleaved timing automatic and manual skew adjust Test patterns at output for system debug Time Stamp feature to capture external trigger Programmable gain, offset, and tAD adjust feature 1:1 non-demuxed or 1:2 demuxed LVDS outputs Applications
3G/4G Wireless Basestation
Receive Path DPD Path Wideband Microwave Backhaul RF Sampling Software Defined Radio Military Communications SIGINT RADAR / LIDAR Wideband Communications Consumer RF Test and Measurement
Отправлено: 12.12.11 17:05. Заголовок: Driving High Speed A..
Driving High Speed ADCs with the LMH6521 DVGA for High IF AC-Coupled Applications Texas Instruments Application Note 2195 Vong Philavanh November 16, 2011 Sampled data systems can be categorized into two main types. The first and simplest is the baseband system known as the “1st Nyquist-zone” system. The second is a more complex under-sampled system, often referred to as the subsampled system or Intermediate frequency (IF)-sampled system. ------------------ Baseband system applications are generally DCcoupled while the IF-sample systems applications tend to be AC-coupled. ----------------------------
In this application note, the LMH6521 is combined with National Semiconductor's high-speed analog-todigital convertor (ADC), the ADC16DV160, that is optimized for an IF frequency of 192 MHz.
17.2.1.1 Dual Edge Sampling Pin (DES) The Dual Edge Sampling (DES) Pin selects whether the ADC12D1800RF is in DES Mode (logic-high) or Non-DES Mode (logic-low). DES Mode means that a single analog input is sampled by both I- and Q-channels in a time-interleaved manner.
Отправлено: 22.12.11 21:58. Заголовок: The EV10AS150A combi..
The EV10AS150A combines a 10-bit 2.5 Gsps fully bipolar analog-to-digital converter chip, driving a fully bipolar DMUX chip with selectable Demultiplexing ratio (1:2) or (1:4). The 5 GHz full power input bandwidth of the ADC allows the direct digitization of up to 1 GHz broadband signals in the high IF region, in either L_Band or S_Band. ############################################################## The EV10AS150A features 7.8 effective bit and close to –58 dBFS spurious level at 2.5 Gsps over the full 1st Nyquist for large signals close to ADC Full Scale (–1 dBFS), and 8.1 bit ENOB at –6 dBFS in the 2nd Nyquist zone.
• 5 GHz Full Power Input Bandwidth (–3 dB) • ±0.5 dB Band Flatness from 10 MHz to 2.5 GHz • Input VSWR = 1.25:1 from DC to 2.5 GHz • Bit Error Rate: 10–12 at 2.5 Gsps
Отправлено: 28.12.11 13:14. Заголовок: e2v and SP Devices w..
e2v and SP Devices working together to deliver the ultimate in high-performance ADC solutions December 13, 2011 -- e2v and SP Devices today announced their collaboration in the provision of high-performance Analogue-to-Digital (ADC) solutions. With the unique combination of the market's fastest 12-bit ADC core speed from e2v, and cutting-edge digital post-processing technology from SP Devices, system designers now have access to never before seen ADC solutions.
This new resource is offered following market demand for more complete joined-up services to design teams. This solution from e2v and SP Devices provides an all-European ADC capability to deliver against designers' exacting requirements across a number of industries including test & measurement, military, and communications.
As an example, with their recently released EV12AS200, a 1.5 GSPS 12-bit ADC, e2v is introducing a true single-core device that, when combined with SP Devices ADX4 time-interleaving technology, enables 12-bit resolution at an unprecedented 6 GSPS. ####################################################################
"We are very excited about this collaboration with e2v", said Ulrik Lindblad, co-founder of SP Devices. "The combination of SP Devices' time-interleaving and linearization technology with e2v's impressive high-performance ADCs offers customers the ability to grow their business, stay ahead of competition, and enter new exciting markets."
"SP Devices' performance enhancing technologies and digitizers are well recognized in the industry," said Nicolas Chantier, Product Marketing Manager for e2v's broadband data converter group, adding "The key to achieving genuine performance breakthroughs in terms of resolution and sampling rate is precisely this unique combination of technology from e2v and SP Devices. Customers can now benefit from the coordinated support of both companies to reach the highest possible performance levels."
About e2v
e2v is a leading global provider of specialist technology for high performance systems and equipment; delivering solutions, sub-systems and components for specialist applications within medical & science, aerospace & defence, and commercial & industrial markets.
e2v is headquartered in the UK, employs approximately 1500 people, has design and production facilities across Europe and North America, and has a global network of sales and technical support offices. For the year ended 31 March 2011, e2v reported sales of Ј229m and is listed on the London Stock Exchange. For more information visit e2v.com.
About SP Devices
SP Devices (Signal Processing Devices Sweden AB and Signal Processing Devices Inc.) provides digital signal
processing IP for the enhancement of analogue-to-digital conversion and high speed digitizers. The IP products are available for implementation in ASICs or deployed on FPGA platforms. SP Devices' portfolio of products enables customers to build systems with state-of-the-art analogue-to-digital performance that enables advances in the areas of Test and Measurement, software defined radio, radio base station transceivers, digital imaging, high-speed data acquisition and broadband communication.
Additional company and product information is available at www.spdevices.com.
e2v and SP Devices working together to deliver the ultimate in high-performance ADC solutions date added : 12 December 2011
e2v and SP Devices today announced their collaboration in the provision of high-performance Analogue-to-Digital (ADC) solutions. With the unique combination of the market’s fastest 12-bit ADC core speed from e2v, and cutting-edge digital post-processing technology from SP Devices, system designers now have access to never before seen ADC solutions.
This new resource is offered following market demand for more complete joined-up services to design teams. This solution from e2v and SP Devices provides an all-European ADC capability to deliver against designers’ exacting requirements across a number of industries including test & measurement, military, and communications.
As an example, with their recently released EV12AS200, a 1.5 GSPS 12-bit ADC, e2v is introducing a true single-core device that, when combined with SP Devices ADX4 time-interleaving technology, enables 12-bit resolution at an unprecedented 6 GSPS.
“We are very excited about this collaboration with e2v”, said Ulrik Lindblad, co-founder of SP Devices. “The combination of SP Devices’ time-interleaving and linearization technology with e2v’s impressive high-performance ADCs offers customers the ability to grow their business, stay ahead of competition, and enter new exciting markets.”
“SP Devices’ performance enhancing technologies and digitizers are well recognized in the industry,” said Nicolas Chantier, Product Marketing Manager for e2v’s broadband data converter group, adding “The key to achieving genuine performance breakthroughs in terms of resolution and sampling rate is precisely this unique combination of technology from e2v and SP Devices. Customers can now benefit from the coordinated support of both companies to reach the highest possible performance levels.”
e2v is a leading global provider of specialist technology for high performance systems and equipment; delivering solutions, sub-systems and components for specialist applications within medical & science, aerospace & defence, and commercial & industrial markets.
e2v is headquartered in the UK, employs approximately 1500 people, has design and production facilities across Europe and North America, and has a global network of sales and technical support offices. For the year ended 31 March 2011, e2v reported sales of £229m and is listed on the London Stock Exchange. For more information visit e2v.com.
About SP Devices
SP Devices (Signal Processing Devices Sweden AB and Signal Processing Devices Inc.) provides digital signal
processing IP for the enhancement of analogue-to-digital conversion and high speed digitizers. The IP products are available for implementation in ASICs or deployed on FPGA platforms. SP Devices’ portfolio of products enables customers to build systems with state-of-the-art analogue-to-digital performance that enables advances in the areas of Test and Measurement, software defined radio, radio base station transceivers, digital imaging, high-speed data acquisition and broadband communication.
Additional company and product information is available at www.spdevices.com.
Отправлено: 28.12.11 17:11. Заголовок: TEK MICROSYSTEMS COM..
TEK MICROSYSTEMS COMBINES ULTRA HIGH SPEED ADC AND DAC WITH HIGHEST DENSITY FPGA PROCESSING 1 month 1 week ago → New Products The new Calypso-V6 Two or Six Channel 12-bit ADCs with Up To 3.6 GSPS per Channel The new Calypso-V6 Two or Six Channel 12-bit ADCs with Up To 3.6 GSPS per Channel (click image to zoom by 1.4x) The new Calypso-V6 Two or Six Channel 12-bit ADCs with Up To 3.6 GSPS per Channel The new Calypso-V6 Two or Six Channel 12-bit ADCs with Up To 3.6 GSPS per Channel (click image to zoom by 4.1x)
Washington, DC – November 15, 2011 – At the 48th Annual AOC International Symposium and Convention, TEK Microsystems, Incorporated, the leading supplier of VME and VXS-based signal acquisition, generation and FPGA-based processing products, has announced the latest member of our QuiXilica product family. The new Gemini-V6 supports either one 12-bit analog-to-digital converter (ADC) input channel at 3.6 GSPS (Gigasamples per second) or three input channels at 1.8 GSPS, combined with a 12-bit DAC output channel operating at up to 4.0 GSPS. Like all members of the QuiXilica-V6 VME / VXS family, the Gemini-V6 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS based systems and combines the highest density FPGA processing available in any 6U form factor with the ultimate in ultra wide band ADC signal acquisition and DAC signal generation for advanced Electronic Warfare applications.
“Tekmicro is committed to providing our customers with the best available ADC and DAC technology for 10, 12, and 16 bit resolutions. The new Gemini-V6 is another industry first for Tekmicro, combining the fastest available sampling rate for 12-bit signal acquisition with a 4 GHz DAC signal output in a 6U VME / VXS form factor”, comments Andrew Reddig, President / CTO of Tekmicro. “By integrating ultra high speed ADC and DAC technology with high density FPGA processing, we are able to meet our customers’ requests for a modular COTS building block with ultra low input-to-output latency, enabling the most advanced DRFM-based EW applications.”
Gemini-V6 Supports Ultra Wide Band Signal Acquisition and Generation
Gemini-V6 is based on the National Semiconductor ADC12D1800RF device which supports either a pair of channels in non-interleaved mode or a single channel using 2:1 interleaved sampling. Gemini-V6 contains two ADC devices, supporting a total of either three channels plus trigger at 1.8 GSPS or one channels plus trigger at 3.6 GSPS, plus a separate 12-bit DAC output channel based on the Euvis M653D which operates at up to 4.0 GSPS.
Gemini-V6 also includes sample-accurate trigger synchronization in all modes, allowing synchronization of input and output channels as well as coherent processing for N-channel algorithms both within a single card and across multiple cards. GPS and timestamp inputs are also available to support precise timing and geolocation.
High Density FPGA Processing
The Gemini-V6 contains two front end FPGA devices, one attached to the ADCs and one to the DAC. The front end FPGAs can be configured with LX240, SX315, or SX475 devices, providing both the highest FPGA processing density available in any 6U form factor today as well as the only VME / VXS platform supporting Virtex-6 FPGAs.
The two front end FPGAs are supplemented with a “backend” FPGA which can be used for additional processing or for backplane or front panel communications. The backend FPGA can also be configured with a range of Xilinx Virtex-6 FPGA options, from the standard LX240 up to a SX475, depending on application requirements.
Memory, Network and Interconnect Resources
The Gemini-V6 includes six banks of DDR3 memory with total capacity of 5 GB and aggregate throughput of 32 GB/s, supporting a wide range of signal processing algorithms with deep memory buffering of the entire signal acquisition stream. The backend FPGA also has two banks of QDR-II memory available for applications that require memory with lower random access latency. Each FPGA supports a Gigabit Ethernet interface for control plane purposes, along with a range of front panel and backplane I/O connections for high speed communications with other processing cards. Gemini-V6 provides an onboard Gigabit Ethernet switch for network connectivity between the front panel, backplane interface, and all onboard FPGAs.
System Management
The Gemini-V6 is based on Tekmicro’s QuiXilica-V6 baseboard which provides the tools necessary for reliability, availability and maintainability in deployed applications. A dedicated system management processor can be used to monitor power and thermal sensors, and is also responsible for managing FPGA initialization and bitstream management. Tekmicro’s QuiXstart technology, included in QuiXilica products since 2005, supports FPGA bitstreams using either onboard flash memory or offboard network resources to support secure applications while maintaining hardware in a sanitized state.
Ruggedization Support for Deployed Applications
The Gemini-V6 is available for a wide range of operating environments, including commercial grade, rugged air and conduction cooled, allowing the card to be used for both laboratory and deployed requirements in both VME and VXS systems.
Comprehensive Developers Kit Speeds Time To Market
The Gemini-V6 is supported by a comprehensive Developer’s Kit that includes interface IP cores for all onboard resources along with Tekmicro’s QuiXtream network toolkit for rapid application development using network-enabled FPGAs. Reference designs are included, with source code, to support quick prototyping of user applications with minimal learning curve.
The Gemini-V6 will be available in for early access customers starting in January 2012.
About TEK Microsystems, Incorporated.
Founded in 1981 and headquartered in Chelmsford, Massachusetts, Tekmicro designs, manufactures and delivers a wide range of advanced high-performance boards and systems for embedded real-time signal acquisition, generation, processing, storage and recording. Tekmicro provides both commercial and rugged grade products which are used in real-time systems designed for a wide range of defense, intelligence and industrial applications such as C4ISR, signals intelligence, electronic warfare and radar. For additional information see www.tekmicro.com. Source: TEK Microsystems Inc
Отправлено: 28.12.11 17:30. Заголовок: FORM B - PROPOSAL SU..
FORM B - PROPOSAL SUMMARY PROPOSAL NUMBER: 09-2 S1.02-9911 PHASE 1 CONTRACT NUMBER: NNX10CD96P SUBTOPIC TITLE: Active Microwave Technologies PROPOSAL TITLE: High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems
SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone) Ridgetop Group, Inc. 6595 North Oracle Road Tucson, AZ 85704 - 5645 (520) 742-3300
PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone) Justin Judkins justin.judkins@ridgetopgroup.com 6595 North Oracle Road Tucson, AZ 85704 - 5645 (520) 742-3300
Estimated Technology Readiness Level (TRL) at beginning and end of contract: Begin: 4 End: 8
TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words) In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming (DBF) systems that will be used in NASA's future radar applications. The ADC will employ a novel combination of time interleaving, high-speed silicon-germanium BiCMOS technology and low-power techniques, such as the double-sampling technique, providing exceptional sampling speed of 500 MSPS, 1.5 GHz analog bandwidth,12 bits of resolution, and below 500 mW power dissipation, exceeding NASA's requirements. Ordinarily, ADC design requires large trade-offs in speed, resolution, and power consumption. The significance of this innovation is that it simultaneously provides a high-speed, high-resolution, and low-power ADC that is well ahead of the state of the art. These three characteristics are needed for DBF systems that contain large ADC arrays. The power consumption of existing ADC chips prohibits implementation of large DBF arrays in space. Ridgetop's innovative design leverages newer semiconductor process technologies that combine silicon and germanium into a compound semiconductor. Ridgetop has identified two Phase 2 objectives, which are: 1. Design, fabricate and characterize Test Chip 1 that contains critical ADC subcircuits. 2. Design, fabricate and characterize Test Chip 2 that contains the complete radiation tolerant, digitally calibrated, time-interleaved ADC design. During Phase 1 Ridgetop identified the topologies for all of the circuit blocks that will be included on Test Chip 1 and Test Chip 2. Ridgetop has also completed transistor-level designs for the key components on these chips. Estimated TRL at beginning and end of Phase 2 contract: Begin 4; End 8.
POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words) NASA applications include radar, imaging, detectors, space radio astronomy, and communication circuits. Space radar systems stand to benefit from the combination of high resolution and low power of the proposed ADC. The technology is ideal for NASA Jet Propulsion Laboratory's radar research program, UAVSAR program, and many other critical communication circuits.
POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words) Non-NASA commercial applications include: В• Phased arrays for ballistic missile defense (BMD) (the DBF technology is commonly cited as a "huge leap" for radar-based missile defense systems) В• Space-based radar for military/intelligence targets or earthquake detection В• Measurement applications, including pin test electronics on ATE systems В• Space navigation systems В• Conformal arrays for UAVs В• Telecommunications applications, such as software-defined radio В• Medical imaging device manufacturers В• Computer networks, hard disk readout circuits, digital oscilloscopes, etc. ; these applications require 500 MSPS sampling speeds, and the "effective number of bits" (ENOB) used in contemporary converters is <10 bits, and the power dissipation is >2 W В• Power-limited applications, such as laptops, wireless devices and PDAs.
TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.) Guidance, Navigation, and Control Microwave/Submillimeter Radiation-Hard/Resistant Electronics Telemetry, Tracking and Control Form Generated on 08-06-10 17:29
Отправлено: 28.12.11 17:30. Заголовок: FORM B - PROPOSAL SU..
FORM B - PROPOSAL SUMMARY PROPOSAL NUMBER: 09-2 S1.02-9911 PHASE 1 CONTRACT NUMBER: NNX10CD96P SUBTOPIC TITLE: Active Microwave Technologies PROPOSAL TITLE: High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems
SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone) Ridgetop Group, Inc. 6595 North Oracle Road Tucson, AZ 85704 - 5645 (520) 742-3300
PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone) Justin Judkins justin.judkins@ridgetopgroup.com 6595 North Oracle Road Tucson, AZ 85704 - 5645 (520) 742-3300
Estimated Technology Readiness Level (TRL) at beginning and end of contract: Begin: 4 End: 8
TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words) In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming (DBF) systems that will be used in NASA's future radar applications. The ADC will employ a novel combination of time interleaving, high-speed silicon-germanium BiCMOS technology and low-power techniques, such as the double-sampling technique, providing exceptional sampling speed of 500 MSPS, 1.5 GHz analog bandwidth,12 bits of resolution, and below 500 mW power dissipation, exceeding NASA's requirements. Ordinarily, ADC design requires large trade-offs in speed, resolution, and power consumption. The significance of this innovation is that it simultaneously provides a high-speed, high-resolution, and low-power ADC that is well ahead of the state of the art. These three characteristics are needed for DBF systems that contain large ADC arrays. The power consumption of existing ADC chips prohibits implementation of large DBF arrays in space. Ridgetop's innovative design leverages newer semiconductor process technologies that combine silicon and germanium into a compound semiconductor. Ridgetop has identified two Phase 2 objectives, which are: 1. Design, fabricate and characterize Test Chip 1 that contains critical ADC subcircuits. 2. Design, fabricate and characterize Test Chip 2 that contains the complete radiation tolerant, digitally calibrated, time-interleaved ADC design. During Phase 1 Ridgetop identified the topologies for all of the circuit blocks that will be included on Test Chip 1 and Test Chip 2. Ridgetop has also completed transistor-level designs for the key components on these chips. Estimated TRL at beginning and end of Phase 2 contract: Begin 4; End 8.
POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words) NASA applications include radar, imaging, detectors, space radio astronomy, and communication circuits. Space radar systems stand to benefit from the combination of high resolution and low power of the proposed ADC. The technology is ideal for NASA Jet Propulsion Laboratory's radar research program, UAVSAR program, and many other critical communication circuits.
POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words) Non-NASA commercial applications include: В• Phased arrays for ballistic missile defense (BMD) (the DBF technology is commonly cited as a "huge leap" for radar-based missile defense systems) В• Space-based radar for military/intelligence targets or earthquake detection В• Measurement applications, including pin test electronics on ATE systems В• Space navigation systems В• Conformal arrays for UAVs В• Telecommunications applications, such as software-defined radio В• Medical imaging device manufacturers В• Computer networks, hard disk readout circuits, digital oscilloscopes, etc. ; these applications require 500 MSPS sampling speeds, and the "effective number of bits" (ENOB) used in contemporary converters is <10 bits, and the power dissipation is >2 W В• Power-limited applications, such as laptops, wireless devices and PDAs.
TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.) Guidance, Navigation, and Control Microwave/Submillimeter Radiation-Hard/Resistant Electronics Telemetry, Tracking and Control Form Generated on 08-06-10 17:29
The ECHO design utilized the Astrium spacecraft bus, had a baseline antenna size of 2 m x 13.8 m, and was designed to fit within the Dnepr launch vehicle fairing. To increase the performance margin the InSAR mission is baselining a larger SAR antenna compared to ECHO. The Spectrum Astro SA-200HP bus was examined for the InSAR mission. The resulting preliminary Flight System configuration included accommodation of the larger (2.5 m x 13.8 m) InSAR antenna and met the Delta II 2920-10 payload fairing volume constraints. The Ball Aerospace BCP 2000 bus was also examined for the InSAR mission. This configuration included the larger SAR antenna (2.5 m x 13.8 m) and preliminary analysis indicates the design can meet the Delta II 2920-10 payload fairing volume constraints. Previous studies and the InSAR industry survey effort give high confidence in the ability to accommodate the InSAR payload on a commercial spacecraft bus.
str 51/62 ########### 4.10.2 L-band Transceiver The L-band Transceiver takes the IF chirp generated at 142.5 – 222.5 MHz and upconverts it to L-band (1220 – 1300 MHz) with a local oscillator of 1440 MHz (thus inverting the spectrum). Using this high-side LO mixing scheme produces no mixing intermodulation products in the L -band chirp. In the Receive chain, it is desirable to avoid requiring very sharp filters since they are more sensitive to phase vs. temperature variations, and are more bulky. So, the L-band filter is generous and its purpose is to only limit possible interference and noise into the receiver. With an LO of 1320 MHz (again inverting the spectrum) the resulting baseband frequency range of 22.5 to 102.5 We chose an offset video frequency range of 22.5MHz to 102.5MHz to be digitized at 250MSps
The ECHO design utilized the Astrium spacecraft bus, had a baseline antenna size of 2 m x 13.8 m, and was designed to fit within the Dnepr launch vehicle fairing. To increase the performance margin the InSAR mission is baselining a larger SAR antenna compared to ECHO. The Spectrum Astro SA-200HP bus was examined for the InSAR mission. The resulting preliminary Flight System configuration included accommodation of the larger (2.5 m x 13.8 m) InSAR antenna and met the Delta II 2920-10 payload fairing volume constraints. The Ball Aerospace BCP 2000 bus was also examined for the InSAR mission. This configuration included the larger SAR antenna (2.5 m x 13.8 m) and preliminary analysis indicates the design can meet the Delta II 2920-10 payload fairing volume constraints. Previous studies and the InSAR industry survey effort give high confidence in the ability to accommodate the InSAR payload on a commercial spacecraft bus.
str 51/62 ########### 4.10.2 L-band Transceiver The L-band Transceiver takes the IF chirp generated at 142.5 – 222.5 MHz and upconverts it to L-band (1220 – 1300 MHz) with a local oscillator of 1440 MHz (thus inverting the spectrum). Using this high-side LO mixing scheme produces no mixing intermodulation products in the L -band chirp. In the Receive chain, it is desirable to avoid requiring very sharp filters since they are more sensitive to phase vs. temperature variations, and are more bulky. So, the L-band filter is generous and its purpose is to only limit possible interference and noise into the receiver. With an LO of 1320 MHz (again inverting the spectrum) the resulting baseband frequency range of 22.5 to 102.5 We chose an offset video frequency range of 22.5MHz to 102.5MHz to be digitized at 250MSps
4.11.2 Science Acquisition ADC A high sampling rate ADC (Analog-to-Digital Converter) was investigated for conversion of the analog offset video receive signal into a digital stream. The goal was to identify a fairly high speed, low power ADC for InSAR science data acquisition. A minimum sampling rate of 250 MHz is required to sufficiently sample the bandwidth.
80 mgz
T.e . po treb .NASA esli ADC emeet 1.5 GSPS to polosa signala mozet bit maximum 500 mgz ############################################################## nachalnaya w PRO/BMDO Lincoln laboratory C-band radar
Отправлено: 28.12.11 18:28. Заголовок: Digital intermediate..
Digital intermediate frequency receiver module for use in airborne SAR applications Assignee: Sandia Corporation (Albuquerque, NM) ---------------------------------------------------------
BACKGROUND
Fine-resolution, high-performance synthetic aperture radar (SAR) system having real-time image formation capabilities are currently being developed. For example, a system being developed by Sandia National Laboratories has a 4 GHz first intermediate frequency (IF) receiver. A simplified block diagram of the current generation IF receiver is shown in FIG. 1 which has been labeled as prior art.
1. A digital receiver for use in radar systems, comprising: an intermediate frequency (IF) converter to translate a higher frequency 1st IF to a lower frequency 2nd IF; an analog-to-digital converter (ADC); a digital signal processor (DSP) including IF (range) domain and Doppler (azimuth) domain filtering, and at least one phase history data interface; wherein the IF converter translates a given radar 1st IF frequency to a 2nd IF necessary to facilitate sampling and efficient quadrature demodulation, and at least one phase history output interface moves data to an image formation processor or a raw phase history storage subsystem.
5. The invention of claim 1 wherein said second IF frequency is one fourth of the ADC sample frequency. (MAX108 1 gsps) 20. The invention of claim 1 wherein the first IF is at about 4 GHz and the second IF frequency is at about 250 MHz.
The AF202 is fully supported on ApisSys 3U VPX FPGA processing engines, making it ideally suited for test and measurement, Electronic Warfare, Ultra Wideband Radar Receivers or LIDAR applications.
ADC Dynamic Considerations Selecting the Drive Amplifier Based on ADC Dynamic Performance Driving Flash Converters Driving the AD9050 Single-Supply ADC Driving ADCs with Switched Capacitor Inputs Gain Setting and Level Shifting External Reference Voltage Generation ADC Input Protection and Clamping Applications for Clamping Amplifiers Noise Consideratio
Отправлено: 28.12.11 20:19. Заголовок: As in many communica..
As in many communications applications, the defense-electronics industry has been trending toward receivers with more bandwidth and higher dynamic range. Applications in this segment include Signals Intelligence (SIGINT) receivers, as well as radar for military and Homeland Security usage. SIGINT systems can be classified as Communications Intelligence (COMINT, communication between people) or Electronic Intelligence (ELINT, typically radar signals).
Both COMINT and ELINT systems benefit from higher bandwidth, since more information is gathered in a given amount of time. Higher bandwidth in a radar receiver produces greater spatial resolution, which in turn creates the ability to distinguish smaller targets or multiple targets that are clustered together. --------------
Traditionally, 100-200 MSPS high-resolution ADCs have been used in SIGINT and radar receivers. More recently, these systems have employed 12-14 bit converters with sample rates in the 250-500 MSPS range. Current developments are requiring multi-GSPS converters in this same resolution range, which favors time interleaving of multiple monolithic ADCs on the printed circuit board. In this application, the power consumption of each ADC is critical, since some radar receivers may use hundreds of ADCs.
A second trend in defense electronics receivers is toward higher dynamic range, which is predominantly set by the SNR. ---------------------------------------------------------------------------------------------------------------------------------------- Dynamic range defines the receiver’s ability to detect small signals in the presence of large signals.
For example, consider two objects being imaged by a radar system in which the target is further from the antenna than a second object. The closest object will produce the strongest backscatter signal, thereby determining the total gain that can be applied without saturating the receiver. The target signal will be much smaller, and may not be received at all if its magnitude is below the detection threshold set by the dynamic range.
In SIGINT systems, higher dynamic range translates to successful capture and decoding of weaker or more distant signals in the presence of interference (either natural or man-made), thereby providing more advanced warning of threats. A low power, high SNR, 14-bit, 500 MSPS ADC, such as the ISLA214P50IRZ from Intersil -- with built-in support for time-interleaved systems -- is an enabling technology for the defense electronics industry, especially SIGINT and radar.
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