An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ###########################
Отправлено: 17.10.10 17:13. Заголовок: Mozno realizowat na ..
Mozno realizowat na imejsucheesja w Rossii nalichii staroj 0.13 micron ( 0.09 toze werojatno est i 0.065 ozidaetjsa 0.065 eto vektornij processor na odnom chipe -100 gigaflop ot NEC SX-9 ,resultat oktjabrja 2007 goda)
Отправлено: 17.10.10 17:23. Заголовок: For direct conversio..
For direct conversion, there are several other considerations that must be made. First, a lower sample rate is likely. Since two converters are required, it is likely that a lower sample rate is used to keep digital processing and power as low as possible. A sample rate of 61.44 MSPS is likely, providing a full 61.44 MHz of complex bandwidth. If it is assumed that the ADCs keep the same input range, a 3 dB increase is allowable since the IQ splitter also divides the power between the two ADCs in addition to the losses associated with a typical frequency translation stage. Without this additional gain, 3 dB (approximately) of ADC range will be lost. In the digital processing, these signals are again summed and produce an overall signal 3 dB higher along with a 3 dB higher ADC noise floor from the noncorrelated ADC noise floor of both ADCs. At the same time, however, the effective ADC input range is also 3 dB higher as is the noise floor of the effective ADC contributions. This results in a first-order wash in sensitivity as signal levels and noise each increase by the same amount. If the signal path includes the extra 3 dB gain, the IP3 requirements increase a proportionate amount. First order, each single ADC must also meet the same requirements for IF sampling. Although the sample rate is lower than may have otherwise been used for IF sampling, the noise bandwidth is equal to the full sample rate. The result is that the noise performance is similar to that of an IF sampling solution operating at 122.88 MSPS with two added advantages. First, because the analog signals are at baseband, clock jitter is no longer a problem. Second, because the analog signals are at baseband, they are not subjected to input slew rate limitations of the converter, which is one of the biggest causes of poor harmonic distortion in IF sampling systems. The primary focus thus far has been to provide a fixed gain solution that meets the dynamic range requirements. This requires a delicate balance between placing the ADC noise sufficiently below the receiver analog thermal noise without overdriving the ADC. As discussed earlier, a converter with a minimum SNR of 68.4 dB makes this possible.
For baseband sampling, the AD9238 and AD9248 dual, 12-bit and 14-bit converters are available. These devices are pin compatible and allow assembly options for platforms that may be common between single and multicarrier applications and where export/import restrictions may exist. In addition to these pin-compatible devices, new quad ADCs are available, including the AD9228 and AD9229. These quad, 12-bit converters are ideal for diversity baseband IQ sampling or for quad, low IF sampling applications such as phased array antennas.
Отправлено: 17.10.10 17:27. Заголовок: There are a number o..
There are a number of approaches to capture the distortion. One approach mixes the transmitted signal down close to dc and uses a high speed ADC to sample a bandwidth that is equal to the order of distortion times the bandwidth of the RF spectrum. A Nyquist band of 75 MHz and 100 MHz is required for three and four carriers respectively. Common sample rates of between 170 MHz and 210 MHz are used for this function (see Figure 15a). An alternate approach mixes down to a low intermediate frequency (IF) and undersamples the transmitted signal. With this approach, the ADC samples the signal and the third-order distortion components without aliasing; the fifth- and higher order distortion terms are allowed to alias over the third-order terms and compensated by coefficient control (see Figure 15b). For four carriers at 153.6 MHz, a 122.88 MSPS converter is needed. The ADC limitation is that it must introduce less distortion than the distortion being measured at the antenna and have a noise spectral density less than the antenna wideband emission requirements. The ADC noise can be averaged over multiple samples, relaxing the noise requirements of the ADC by the oversample ratio to typically 8 ENOB to 10 ENOB. The following discussion reveals a required noise level at 10 MHz offset is –30 dBm/1 MHz or –90 dBm/Hz. This level must be attenuated by typically 50 dB to reduce the maximum PA output to that of the ADC full scale; the directional coupler typically has about 40 dB of attenuation. Therefore, the spectral density at the ADC input is –140 dBm/Hz; across a 100 MHz Nyquist band, this corresponds to an ADC SNR of about 60 dB. The AD9430 provides mid 70s SFDR up to 200 MHz and an SNR of mid 60s, meeting these requirements.
ATMEL’s TS8388 ADC Jitter • According to ATMEL’s TS8388 ADC data-sheet (1GS/s, 8-bit & ENOB=7.1-bit), cited by Bill Jones, JAPJ=0.6 ps JCLK=0.5 ps. • Assuming JAIN=0.5 ps then JADC=0.93 ps • From formula ENOB=7.4-bit • High-speed ADC ENOB’s are jitter limited ##################################### • GS/s, ENOB > 6.5-bit ADCs are hard to integrate on a VLSI CMOS chip due to excess recovered clock’s jitter ##################################### • Recovered clock period: 1200 ps (PAM-10), 800 ps (PAM-5)
High-Resolution Mode: The High-Resolution Mode is an 80 MHz mode that trades swath coverage for increased resolution (10 m). One of seven beams may be chosen in this mode; each with a swath width of ~40 km. Operation in this mode would be in lieu of the primary 35 m resolution Stripmap Mode and would be performed intermittently at the request of the Science Team when targets of interest requiring higher resolution are identified
The current InSAR baseline eight-day sun-synchronous orbit at 760 km altitude yields a separation of ~340 km at the equator between adjacent nadir tracks, as shown in the following figure. In order to meet the requirement for complete global access the InSAR Payload System will be designed such that the accessible area (viewable swath) is greater than or equal to 340 km.
Multiple A/Ds versus a single one: pushing high-speed A/D converter SNR beyond the state of the art Thomas Neu and Grant Christiansen, Texas Instruments. Inc.
7/4/2007 5:54 PM EDT (Note: an edited version of this article appeared in Planet Analog magazine, June 24, 2007. This online version includes formulas and derivations that did not appear in the print version.)
The wireless communications field is constantly demanding faster and higher resolution high-speed data converters to enable them to process more bandwidth (allowing more channels) with greater resolution. One way to further advance state-of-the-art analog-to-digital converters (ADC) is to average multiple high-speed ADCs to increase the dynamic range. With two ADCs, for example, the overall signal-to-noise ratio (SNR) can be improved by up to 3 dB; with three converters, it can be as much as 4.8 dB. --------------------------------------------------------------------------------------------
Theoretically, the SNR can be increased by 3 dB (one-half-bit) with two different methods. ------------------------------------------------------------------------------------------------------- One option is to double the sampling rate and digitally filter the output (e.g., with an FIR decimation filter).
The second option is to parallel two ADCs and simply average the digital output.
At times, doubling the sampling rate is the less desirable option because faster ADCs may not yet be available. They may also start out with a lower SNR and often times are higher power than two slower ADCs. Furthermore, a faster sampling clock with low jitter is required. --------------------------------------------------------------------------------------------------------------------------------------------------
This article shows the actual results of combining three TI ADS5546 converters (14-bit, 190 Msps), using the second option of paralleling the ADCs, and it addresses the clock jitter requirement which engineers face with the implementation. ------------------------------------------------------------------------------------------------------
Setup The concept of averaging the output of separate ADCs for SNR improvement was verified using three ADCs tied to an FPGA, which then outputs the conversion results of each individual ADC or two or three ADCs averaged together, Figure 1.
By using three ADCs instead of one, the SNR ideally improves by 4.8 dB, as derived below, which boosts the 14-bit ADC (SNR ∼74dB) to a 16-bit ADC ################################################################################################## level (SNR ∼79dB). #############
Ostanetsja li wse ostlanoe ? W predleax trebowanij
Esli da .to mozno wzjaz 3 12 bit po 1-1.8 gsps i poluchit 14 bit s input frequency 1000 mgz
AFAR PAK FA/ F-22 imeet 2 rezima SAR ,gde trebuetsja takaja polosa pri neuschej 8 -10 ghz
1. SAR s rar .sposobnostju 250 mm na suche 2. Poisk periskopa PLA
Odno preobrazowanei chastoti i srazu AZP
Po nekotorim publichnim dannim w PAtriot PAC-3 16 bit AZP
The analog input signal was split and fed into three ADCs which were sampled with a common clock source. An FPGA performed the averaging function as well as a level translation of the digital output from DDR-LVDS to LVTTL (double-data-rate, low-voltage differential signal to low-voltage TTL).
Figure 1: Block Diagram of System to Average Multiple ADC Outputs (Click to enlarge image)
The averaging technique reduces uncorrelated white noise, but has no effect on distortions inherent to the ADC design that might be common to all three ADCs. If, for example, the ADC creates a large third-order distortion product, it will show up in each ADC used and averaging won't reduce it. Therefore, averaging only improves SNR, but not spurious free dynamic range (SFDR).
The formulas and derivations used to determine the maximum SNR gain for the two methods described above (doubling the sample rate and averaging multiple ADCs) are discussed in the addendum at the end, "Theory."
Measurements In order to verify the SNR gain, a board was designed containing three ADS5546 ADCs (14-bit, 190 Msps) and an FPGA that was used to perform a 3:1 averaging function. Using two or three standalone ADC evaluation modules (EVM) for this experiment usually doesn't work as well, because noise coupled into the cable assembly is correlated and, therefore, doesn't average out. Furthermore, if the cables are not matched very well, skew between ADCs adds phase mismatch and further degrades the overall SNR.
Unfortunately, the chosen input matching network design was not optimized. The trace impedance was not adjusted properly to the transformer and the split input traces were not properly matched. Due to this input mismatch, the input signal was attenuated at frequencies above 60 MHz with one exception. Around 150 MHz, the input circuitry seemed to work very well. Therefore, some of the measurements were taken with an input amplitude as low as -6 dB, and were mathematically adjusted to -1 dB full scale (FS) afterwards in the following manner.
First, with only one ADC active, the SNR performance was measured and compared to the ADS5546 data sheet performance at the lower input amplitude. Then the measurement with three ADCs active was adjusted by the difference. This adjustment seems justified as the 150 MHz data point is right in line with the resulting values, Figure 2.
Figure 2: SNR Comparison between ADS5546 Data Sheet Values, Single ADC and Triple ADC (Click to enlarge image)
The adjusted measurements show a consistent 4-or-greater dB improvement across various input frequencies when comparing it to 'single ADC' data. Even at the higher input frequencies, the measured and calibrated values within one-half dB of the theoretical values with the exception of device number three. The noticeable SNR roll-off is due to the clock-jitter limitation which is prevalent in any ADC, as derived in the next section.
Clock jitter requirements The final SNR at the output depends on the input frequency and is primarily limited by the thermal noise of the ADCs and the aperture jitter of the sampling clock.
As derived earlier, averaging the SNR of three ADCs improves all uncorrelated noise sources by ∼4.8 dB which applies to the thermal noise term, as well as the internal aperture jitter of the ADC.
The ADS5546 data sheet lists the following specifications:
•Thermal noise ∼74 dB (=SNR at low input frequency where SNR is thermal noise limited) •Aperture jitter ∼150 femtoseconds (fs)
Therefore, when averaging the outputs of three ADCs sampling the same signal, the overall thermal-noise contribution is reduced from 74 dB to 78.8 dB and the ADC aperture uncertainty from 150 fs to 86 fs (1.50 fs · 10-4.8/20).
The sampling jitter comprises the internal aperture jitter of the ADC and the jitter of the external clock source (common to all three ADCs when averaging).
Отправлено: 20.10.10 12:29. Заголовок: There are also other..
There are also other advantages gained by increasing sampling frequency. Over-sampling signals also enables processing-gain benefits in the digital domain with the use of digital filtering. This is because the ADC noise floor can be spread over a larger output bandwidth.
Doubling the sampling rate, for a fixed input bandwidth, results in a 3 dB improvement in dynamic range. Every further doubling of the sampling frequency provides an additional 3 dB of dynamic range. #########################
Challenges with time interleaving The main challenges with time interleaving are accurate phase alignment of sampling-clock edges between channels, and compensating for manufacturing variations that inherently occur between ICs. Accurately matching the gain, offset and clock phase between separate ADCs is very challenging, especially as these parameters are frequency dependant. ###############################################
Unless precise matching of these parameters is achieved, dynamic performance and resolution will be reduced. The three main sources of error are illustrated in Figure 2. ###############
Time‑interleaving of analog‑to‑digital converters (ADCs) is a way to increase the overall system sample rate by using several ADCs in parallel. The challenge is to handle the mismatch between the individual ADCs, especially at higher frequencies.
Отправлено: 20.10.10 20:42. Заголовок: TRW continues the BM..
TRW continues the BMDO-funded program for the development of infrared (IR) focal plane array (FPA) imaging signal processing circuits, built in NbN and operating at 10 K. The BMDO project is part of the organization's effort to develop an integrated high-performance sensor with higher sensitivity for missile surveillance by developing and integrating high-performance superconducting ADCs and focal plane arrays.
An ADC chip and digital signal processing chip were mounted on a 1.25 inch multi-chip module (MCM) with high bandwidth, low impedance interconnect (s. Fig. 15). The populated MCM is designed to be installed into a module housing for operation with the cryogenic IR FPA. A 12-bit NbN SFQ counting ADC, previously used in a single chip version of the IR focal plane array sensor test system, was now implemented in an improved NbN process which includes a ground plane. Considerable attention has been focused on reducing parasitic inductance to compensate for the high characteristic inductance of the NbN films. These design improvements increase operating margins and circuit yield and make the ADC more robust in the presence of external system noise. Data from a bit-serial subtraction circuit to be used for pixel-by-pixel background subtraction were also presented.
The simultaneous high performance and ultra low power dissipation of superconducting circuits enables a long wavelength IR focal plane array sensor architecture featuring A/D conversion and digital signal processing in the cryogenic space very near, or on the focal plane. Sensors designed to detect long wavelength IR radiation (~ 25 µm) must operate at temperatures below 15 K in order to have low enough detector thermal noise. This requirement for cryogenic operation means an existing long wavelength sensor system can accommodate NbN superconducting circuits operating at 10 K without requiring a major system redesign. Performing A/D conversion followed by digital signal processing to enhance the signal-to-noise ratio and reduce the total data rate results in significant system-level payoff.
TRW previously operated a 10 K, 12-bit, 2 MSps NbN ADC as part of a long wavelength IR focal plane array sensor demonstration (ISEC’97). In that demonstration, a 128 x128 long wavelength IR focal plane array was read out at 100 frames per second, producing IR images of room temperature objects against a cooled background, with all the data converted by a single NbN ADC dissipating 0.3 mW.
The next step in the technology development is to demonstrate a system in which the first of the appropriate digital signal processing (DSP) functions is implemented in NbN circuitry and integrated with the ADC in the 10 K package. The circuit and packaging results reported at ASC’98 represent significant progress toward that goal.
Отправлено: 21.10.10 21:06. Заголовок: in a flash ADC the n..
in a flash ADC the number of comparators increases by a factor of 2 for every extra bit of resolution; simultaneously, each comparator must be twice as accurate #########################################################################################################
Отправлено: 21.10.10 22:05. Заголовок: powtor High resolu..
powtor
High resolution is particularly important in applications like imaging radar that must discern small objects close by ######################################################################### large objects, or in signals intelligence that must be able to characterize even the faintest radio signals in the presence of many other signals and electronic noise. ############################
Noise and distortion rejection is measured in two ways. The first is spurious noise dynamic range (SNDR), and the second is signal to noise ratio (SNR), both of which are measured in decibels, or dB. The higher the dB level of these two measurements, the better the A/D or D/A is at detecting and characterizing weak signals that may be important. Strong noise and distortion rejection is particularly important for applications like signals intelligence, radio communications, or sophisticated radar jammers.
he larger the application, the more the designer concentrates on pure A/D and D/A converter performance, rather ########################################################################### than on device size and power consumption says Pam Aparo, ######################################### marketing manager for device maker Analog Devices High-Speed ADC Products segment in Greensboro, N.C. "Most of the requirements we get break down into 'the sky's the limit' in the performance and power that our users need," she says. "A ground-based radar is not concerned about power; they want all the performance they can get. ####################################################################### With missiles and communications and things people have to carry, it has to be a lightweight system, so we have to get the size and power down." #####################
No A/D or D/A converter -- at least not yet -- can be all things to all people. One rule of thumb is the faster the ######################################################################### device, the lower its resolution and noise rejection. On the other hand, the devices with the finest resolution and noise ########################################################################## rejection typically are not the fastest devices. It all depends on the application and the designer's needs. ######################################################################
One kind of radar jammer, for example, might have a high priority on speed, at the expense of resolution. ###################################################################### Above all, this system may need to detect radar signals quickly so it wastes no time in overwhelming the enemy ########################################################################### signal with jamming energy. In this application, it is not so important to characterize the radar signal with fine ####################################################################### resolution as it is to detect the radar signal quickly and jam it. ########################################
Signals intelligence and radio communications, on the other hand, put a priority on high resolution to detect and ########################################################################## classify weak signals of interest -- particularly when the desired signals are alongside strong signals or strong sources of noise. ########
A/D converter manufacturers like National Semiconductor in Santa Clara, Calif., Intersil, and others are pursuing interleaving technology, while others around the industry do not give this design approach much credence. ###################################################################### "People have tried ganging A/Ds together," says Rodger Hosking, vice president of signals intelligence and software defined radio processing specialist Pentek Inc. in Upper Saddle River, N.J. "In practice it is very difficult, and almost never works very well."
Отправлено: 21.10.10 22:18. Заголовок: powtor ot National a..
powtor ot National about 3.6 gsps/12 bit interleaved in one chip
Of course, to get these very high speeds you can time interleave multiple converters. One competitor has interleaved four 550 MSPS ADCs to get to 2 GSPS but this is quite a complex solution. It is difficult to design this at board level and it consumes quite a lot of power. In half the board area (which has cost implications) we can achieve almost twice the speed and the power consumption is half. And we have one chip compared to four so we offer a lot of advantages for designers.
Waveform Variations by Mode.Although the specific waveform is hard to pre-
dict, typical waveform variations can be tabulated based on observed behavior of a number of existing A-S radar systems. Table 5.1 shows the range of parameters that can be observed as a function of radar mode. The parameter ranges listed are PRF, pulse width, duty cycle, pulse compression ratio, independent frequency looks, pulses per coherent processing interval (CPI), transmitted bandwidth, and total pulses in a Time-On-Target (TOT).
Obviously, most radars do not contain all of this variation, but modes exist in many fighter aircraft, which represent a good fraction of the parameter range. Most fighter radars are frequency agile since they will be operated in close proximity to similar or identical systems. The frequency usually changes in a carefully controlled, completely coherent manner during a CPI.8 This can be a weakness for certain kinds of jamming since the phase and frequency of the next pulse is predictable. Sometimes to counter- act this weakness, the frequency sequence is pseudorandom from a predetermined set with known autocorrelation properties, for example, Frank, Costas, Viterbi, P codes.16 A major difficulty with complex wideband frequency coding is that the phase shift- ers in a phase scanned array must be changed on an intra- or inter-pulse basis greatly complicating beam steering control and absolute T/R channel phase delay. Another challenge is minimizing power supply phase pulling when PRFs and pulsewidths vary over more than 100:1 range. MFAR systems not only have a wide variation in PRF and pulsewidth but also usually exhibit large instant and total bandwidth. Coupled with the large bandwidth is the requirement for long coherent integration times. This requirement naturally leads to extreme stability master oscillators and ultra low-noise synthesizers.44
ADVANCED SCIENCE & NOVEL TECHNOLOGY 27 Via Porto Grande Rancho Palos Verdes, CA 90275 Phone: PI: Topic#: (408) 564-9236 Dr. Sean P. Woyciehowsky MDA 07-003 Awarded: 02/13/08 Title: High Performance Rad Hard Analog to Digital Converter Architectures Abstract: Electronic components for future space based radar systems on chip (SOC) must function correctly in natural and radiation filled environments while providing state-of-the-art performance. The corresponding SOC must employ advanced, extra low-power, radiation-hardened (RH), analog-to-digital converters (ADCs) capable of operating at multi-giga sampling speeds. To satisfy the described needs, we propose to develop an ADC block with 9 bits of resolution and up to 10Gs/s of sampling speed. The 9 bit wide data will be demultiplexed by a factor of eight to a rate of 1.25Gb/s for direct loading into a following FPGA where signal processing will be performed. Our patent-pending radiation-hardening techniques incorporate a methodology based on protection and redundancy, which provides both total ionization dose (TID) and single-event upset (SEU) tolerance within the IC. The proposed high performance characteristics of the ADC will be achieved by utilizing an advanced SiGe IC fabrication technology. -----------------------------------------------------------------------------
HITTITE MICROWAVE CORP. 20 Alpha Road Chelmsford, MA 01824 Phone: PI: Topic#: (719) 590-1112 Dr. Michael Hoskins MDA 07-003 Awarded: 02/13/08 Title: High Sample-Rate Ultra-Wideband Track-and-Hold Demultiplexer (2007047) Abstract: Hittite proposes to develop a Radiation-Tolerant Ultra-Wideband Track-and-Hold (T/H) Demultiplexer to address MDA's future needs for microwave signal sampling/data conversion. This development is motivated by the difficulties in achieving high-speed interleaved analog-to-digital converter (ADC) assemblies with good accuracy. -----------------------------------------------------------------------------------------------------------------
A switched-emitter-follower T/H amplifier in the SiGe BiCMOS process with the capability for 15 GHz sampling bandwidth, 6 - 8 Gs/s sample rate, and 8 - 9 bit accuracy will be studied. This high-speed T/H will be used as the front end of a ------------------------------------------------------------------------------------ two-rank T/H sampler/demultiplexer that provides a 2:1 output sample rate reduction, enabling the use of lower rate ADCs in an interleaved assembly without the usual sample timing mismatches that degrade performance. ----------------------------------------------------------------------------------------------------------------------
The T/H demultiplexer can also operate as a subsampler to down convert any Nyquist bands within the 15 GHz bandwidth. This T/H circuit is expected to offer unprecedented bandwidth and operating speed while maintaining accuracy suitable for meeting the X-band and microwave data conversion goals of many military systems. Under Phase I, Hittite will perform a design study with circuit simulations to determine the feasibility and performance of the basic T/H amplifier and the two-rank demultiplexer. Prototype circuits will be built and tested in Phase II.
NU-TREK 17150 Via del CampoSuite 202 San Diego, CA 92127 Phone: PI: Topic#: (909) 864-7858 Mr. William Poland MDA 07-003 Awarded: 02/13/08 Title: Multiplexed, Rad Hard ADC Abstract: The proposed part is a rad-hard, 16-input, 14-bit ADC, with aggregate speed of 200 MSPS. -------------------------------------------------------------------------------------------------------------------- dlj srawnenija 09.2010 National 12 bit 1000 msps ,100 krad
The 16 inputs are sampled individually and can be configured as 16 single-ended inputs or 8 differential inputs. The ADC provides 14 data outputs, a data-ready signal, and an over-range indicator. The digital outputs of the ADC are CMOS low-voltage differential signal (LVDS) outputs. The part will be fabricated using Texas Instruments' BiCom3X, a SOI process with CMOS and complementary SiGe bipolar transistors. SiGe bipolar transistors typically have very high total dose hardness, ------------------------------------------------------------------------------------------------------------------------------------------
and we are not aware of an ELDRS problem. The SOI wells prevent latch-up and restrict the silicon volume that can produce photocurrents from either ionizing dose rates or single event strikes. Our designers, Bill Poland, Jim Swonger, Wayne Dietrich and John Branning, have designed over 140 ASICs, many of them rad-hard. They worked together on a 14-bit rad-hard ADC, on which the proposed part is based. Nu-Trek is an emerging suppler of rad-hard parts, with four parts coming on sale in 2008. The Nu-Det has already been inserted into the MKV and NGIMU. The Clam/NED is slated for insertion in the Army's FCS.
Отправлено: 22.10.10 22:13. Заголовок: However, as discusse..
However, as discussed in the article entitled “A Wide Dynamic Range Radar Digitizer,” [1] converting to the digital domain introduces errors which limit overall system performance.
One of the most important limitations is dynamic range, which is the range of signal amplitudes that can be captured by an ADC. This is determined by the number of conversion bits as well as by the signal-to-noise ratio (SNR) of the analog components (amplifiers, mixers, etc.) which precede the ADC.
Отправлено: 25.10.10 12:05. Заголовок: For example, in mili..
For example, in military radar systems, a single ADC12D1X00 combined with a digital down-converter can replace multiple mixers, filters, amplifiers and local oscillator stages used in traditional heterodyne double- or triple-conversion radio implementations. #####################
Since this new class of SDRs requires the ADC to sample wide-bandwidth signals, a new set of metrics such as noise-floor, NPR and IMD provide the best measure of a system's capability to extract narrowband information from a wideband spectrum.
This is in stark contrast to traditional ADC specifications -- signal-to-noise ratio (SNR), spurious-free dynamic range (SFDR), and effective number of bits (ENOB) -- which focus on single-tone performance in the Nyquist bandwidth and do not provide the best gauge of a system's overall capability.
...and IMD ###########
Dlja ADC!2D1800
DESIQ mode -61 db
1212 mgz ,1217 mgz -54 db
chut lutsche chem SINAD na 1448 mgz -50db ------------------------------------------------------
Отправлено: 25.10.10 12:41. Заголовок: Menee skorostnoj 12..
Menee skorostnoj 12D1000 non des -mode ,1000 megasample -sootw .mozet obrabotat 500 mgz polosu signala protiv 12D1600 non des mode - 800 mgz , 12D1800 non des mode ,1800 megasample ,900 mgz
ENOB 8.6 db 8.6 db 8.4 db 1448 mgz SINAD 53.6 db 53.8 db 52.5 db SNR 54.1 db 55 db 53.1 db SFDR 67 db 61.9 db 60.3 db
Analog–to–Digital Converter Technology and Corresponding Signal Processor Throughput and Dynamic Range. For the PATRIOT radar, advanced signal process technology is required to support dynamic ranges while maintaining the throughput, size, weight, and prime power requirements. Applicable advanced signal processing techniques, such as maximum entropy method (MEM), are required for incorporation into PATRIOT, along with a concept for their utilization, signal processor hardware concepts, and an assessment of their performance improvement over pulse Doppler for various environments.
The PAC–3 radar signal processors currently use 12–bit A/D converters for narrow band actions. For radar performance in clutter, more dynamic range is needed—up to 14–16 bits for wide band. system/transmitter intermediate frequency (S/T–IF) receiver subsystem changes would require the incorporation of 16 bit A/D converters into the PATRIOT S/T–IF receive subsystem, along with the incorporation of the advanced signal processor hardware and processor resident software. Included in the proposed architecture and design is the removal or disabling of the current digital signal processor and the replacement of their functions in the advanced signal processor. The CDI–3 receiver subsystem was designed for later incorporation of 12 bit A/D converters when available. The incorporation of the 14–bit converter will require some redesign of the receiver. The value added for PATRIOT is improved fire unit search, track, and CDI capabilities in low altitude, high clutter or extensive antitactical missile debris environments. The technology infusion period is from 1QFY02 to 4QFY03. [POC: Rodney Sams, PATRIOT, (205) 955–3166]
Отправлено: 25.10.10 15:21. Заголовок: Hall: We did engage ..
Hall: We did engage with one company by the name of Mercury Computer Systems. -----------------------------------------------------------------------------------------------
postawschik Northrop
They build data acquisition cards and essentially the company's creates data acquisition card solutions. The company is focused on military/aerospace applications. What results is a proof of concept through these data acquisition cards and then the company will typically do a custom job for a particular project.
Brian Kimball, Principal HW Engineer at Mercury Computer Systems told us: “We needed a 16-bit, 250-MSPS data converter with 90 db of SFDR for one of our key customer's highly advanced, data acquisition systems. The AD9467 data converter was designed into this customer's system because it met our SFDR, ENOB, and power requirements. Analog Devices worked with us as trusted advisors to provide early-access silicon and design support to enable the timely development of our prototype product.”
What caught MCS' customer's attention was their system's performance based on our ADC. We've been working with Mercury for a couple of quarters now in terms of early engagement and early samples for them. It has been very successful for them.
Tekmicro Supplies Signal Processing System for NASA Glenn Research Center
New Texas Instruments ADS5400 Supports Tekmicro’s Unprecedented Performance ######################################################
on stoit 775 $ w partijax po 100 stuk ,12 bit 1000 megasamles --------------------------------------------------------------------------
Chelmsford, MA – October 26, 2009 – TEK Microsystems, Inc. announced it has shipped follow up system orders to NASA Glenn Research Center in Cleveland, OH. Glenn is developing
a VXS-based satellite communications test set for ground based validation of satellite equipment. The test set will be used ################################################################ for the Tracking and Data Relay Satellite System compatibility testing as part of NASA’s Constellation Program. Successful development will result in additional orders of totaling over $1M.
NASA’s Constellation Program is building the next generation of space vehicles that will take astronauts to low Earth orbit, the moon, and eventually to Mars.
Tekmicro’s Titan-V5 VXS and Callisto VXS boards are now being used in the program. Titan-V5 VXS was selected because of its first-in-the-industry levels of high performance, low latency, and signal integrity.
The Titan-V5 combines four channels of 1 GSPS 12-bit ADCs, four channels of 1.2 GSPS 14-bit DACs and three Virtex-5 FPGAs to provide the highest bandwidth channel count per slot available for VXS products on the market today.
By providing a massive FPGA processing resource at the heart of the VXS communications fabric, Callisto achieves an optimal balance between processing power and IO bandwidth; maximizing the value that can be extracted from the use of FPGAs for signal processing.
“The Titan-V5 utilizes best-in-class devices for digitization and signal generation, and, it redefines low latency by providing almost instantaneous acquisition-to-response times when compared with older architectures using multiple boards or modules,” comments Andy Reddig, CEO/CTO of Tekmicro. “Our ability to implement the newly announced ADS5400 from Texas Instruments gave our engineering team technology with nearly 2x the speed of competitive offerings. The culmination of these advanced technologies gives Titan-V5 a competitive edge for signal processing solutions.”
In addition to Callisto and Titan-V5, Tekmicro offers the broadest range of Xilinx Virtex-5 based streaming I/O and FPGA processing solutions for both analog and digital I/O in the industry today in both commercial and rugged options.
About TEK Microsystems, Incorporated Founded in 1981 and headquartered in Chelmsford, Massachusetts, Tekmicro designs, manufactures and delivers a wide range of advanced high-performance boards and systems for embedded real-time data acquisition, data conversion, storage and recording. Tekmicro provides both commercial and rugged grade products that are used in real-time systems designed for a wide range of defense, intelligence and industrial applications such as C4ISR, SIGINT, EW and Radar.
Tarvos-V5 Overview Designed to meet the needs of demanding sensor-processing applications across a range of environments, the Tarvos-V5 employs three Xilinx Virtex®-5 FPGAs, advanced DDR3 SDRAM, and the highest resolution digital-to-analog and analog-to-digital converter technologies available at a 185 Msps sampling rate.
Each analog input channel uses a Linear Technology LTC2209 16-bit A/D converter, which is designed for digitizing high frequency, wide dynamic range signals within an analogue input bandwidth of 700 MHz. A range of options are available for input signal conditioning to support different receiver applications.
Отправлено: 25.10.10 17:12. Заголовок: The advantages alrea..
The advantages already mentioned include the ability to sample at high IF frequencies. • The disadvantages today include: – The instantaneous bandwidth is still limited by the sampling rate of the A/D. – The dynamic range of the sample and hold is limited at high RF frequencies
Отправлено: 25.10.10 17:27. Заголовок: With our communicati..
With our communication heritage as our proud legacy, LNX is committed to providing mission critical components, multi-function assemblies, transceivers, and digital products that keep our forces and nation out of harm’s way.
Team spirit is alive at LNX as we work together to overcome your system’s design challenges. Over the last decade, LNX has manufactured hardware for some of the most critical initiatives in military and homeland security programs, as well as high level commercial communications projects. Our products have been proudly deployed in military radar and communications, radio astronomy, missile guidance, UAV data links, EW and ECM fighter aircraft, shipboard radar and communications, remote sensing systems, and ground based satellite systems. With our broad range of product expertise, we are able to provide cost effective, highly reliable solutions our customer’s needs ranging from individual components to highly integrated and intricate multi-function assemblies.
Отправлено: 25.10.10 20:03. Заголовок: Dlja radara C band..
Dlja radara C band 5.8 gigagerz ,kotorij ispolzowalsjaw programme Appolo
16 bit ADC podxodjat otlichno
The AN/FPS-16 is a highly accurate ground-based monopulse single object tracking radar (SOTR), used extensively by the NASA manned space program and the U.S. Air Force. The accuracy of Radar Set AN/FPS-16 is such that the position data obtained from point-source targets has azimuth and elevation angular errors of less than 0.1 milliradian (approximately 0.006 degree) and range errors of less than 5 yards (5 m) with a signal-to-noise ratio of 20 decibels or greater.
The radar utilizes a 12-foot (4 m) parabolic antenna giving a beamwidth of 1.2 degrees at the half-power points. The range system utilizes either a 1.0, 0.5, or 0.25-microsecond pulse and the prf can be set by pushbuttons. Twelve repetition frequencies between 341 and 1707 pulses per second can be selected. A jack is provided through which the modulator can be pulsed by an external source. By means of external modulation, a code of from 1 to 5 pulses may be used.
The sum, azimuth, and elevation signals are converted to 30 MHz IF signals and amplified. ***************************************************************************
y sowremennix 16-bit Linear tech,National Semiconductor ,TI i Analog Device
Fin do 300 mhz i 250 megasamle
8mgz polosa-eto minimum 16 megasample
The phases of the elevation and azimuth signals are then compared with the sum signal to determine error polarity. These errors are detected, commutated, amplified, and used to control the antenna-positioning servos. A part of the reference signal is detected and used as a video range tracking signal and as the video scope display. A highly precise antenna mount is required to maintain the accuracy of the angle system.
N/FPS-16 RADAR SET TYPICAL TECHNICAL SPECIFICATIONS ------------------------
Type of presentation: Dual-trace CRT, A/R and R type displays.
Transmitter data - Nominal Power: 1 MW peak (fixed-frequency magnetron); 250 kW peak (tunable magnetron). Frequency Fixed: 5480 plus or minus 30 MHz Tunable: 5450 to 5825 MHz
Pulse repetition frequency (internal): 341, 366, 394, 467, 569, 682, 732, 853, 1024, 1280, 1364 or 1707 pulses per second
Pulse width: 0.25, 0.50, 1.0 µs
Code groups: 5 pulses max, within 0.001 duty cycle limitation of transmitter.
Radar receiver data - Noise Figure: 11 dB Intermediate Frequency: 30 MHz ------------------------------------- Bandwidth: 8 MHz ----------------------- Narrow Bandwidth: 2 MHz Dynamic Range of Gain Control: 93 dB
X-Band Receiver-on-Chip (RoC) Development Based on NLEQ DSP
• Linear dynamic range limited by the final NLEQ IF amplifier – NLEQ DSP to linearize the amplifier and ADC • High performance and low power achieved with new analog/digital co-design paradigm MIT Lincoln Laboratory HPEC 2009-25 WSS 9/23/2009 • Single die receiver implementation being explored
• Linearity enhancement required by DoD/commercial sensor/receiver applications – Phased array sensors/receivers – Frequency channelized sensors/receivers • MIT LL has developed high-throughput low-power nonlinear equalization signal processor ICs – Massively parallel systolic architecture – Polyphase distributed arithmetic processing – Block floating point residue number arithmetic – Full custom low-threshold-voltage dynamic logic • Successful demonstration results – >20 dB linearity improvement – NLEQ4000 Up to 4GSPS, <1.25W Up to 12 bit ADCs – NLEQ500 Up to 500MSPS, <0.25W Up to 18bit ADCs
Nyquist's sampling theorem states that if a signal is sampled at least twice as fast as the highest sampled frequency component, no information will be lost when the signal is reconstructed. The sample rate divided by two (Fs/2) is known as the Nyquist frequency and the frequency range from DC (or 0 Hz) to Fs/2 is called the first Nyquist zone. ####################################################################
Maxim Integrated Products has introduced the MAX109, which the company claims to be the industry's highest-performance, 8bit, 2.2GSps ADC. The device offers excellent wideband dynamic performance that has been optimized for capturing input frequencies in the second Nyquist zone, said Maxim. ##############################################
Fabricated using an advanced SiGe process, MAX109 integrates a high-performance track/hold (T/H) amplifier, a quantizer and a 1:4 demultiplexer on a single monolithic die. At a sample rate of 2.2GSps and an input frequency of 300MHz, the ADC achieves a spurious-free dynamic range (SFDR) of 62dBc and an SNR of 45dB. The SNR remains flat (within 1.6dB) for input frequencies all the way up to 2GHz.
Full-scale SINAD and SNR, though adequate for single-tone input signals, can't provide the complete picture for the myriad signals and broad bands of spectrum present in wideband radios. Multiple-tone testing and SFDR power sweeps are more informative.
Sample rate: Many wide band radios mix down the RF spectrum to baseband (a range of signals from dc to some upper frequency) using wide-dynamic-range, ultra-high-intercept-point mixers such as the AD831 (Analog Dialogue 28-2, pp. 3-5). Converters for such radios require a sample rate at least twice the highest frequency (Nyquist rate), i.e., 20 MSPS minimum for signal range from dc to 10 MHz, and generally with at least 20% additional margin, raising the required encode rate to about 25 MSPS.
Отправлено: 27.10.10 15:07. Заголовок: If wide-bandwidth AD..
If wide-bandwidth ADCs are available, a single down-conversion can be used, as illustrated in Figure 1.2, thus improving the linearity of the receiver. Using such an approach, in a satellite communication system, with an RF 64QAM signal in the 10-30GHz range, one down-conversion results in an IF signal in the 1-3GHz range. In this case, the high-speed ADC must have an input bandwidth of 3GHz with a typical resolution of 8bits*. The sampling frequency of the ADC must be higher than the Nyquist rate to compensate for performance degradation near the Nyquist bandwidth.
*Higher-order modulation schemes (such as 256 QAM) impose more stringent requirements on the SNR performance of the ADC and thus resolution
Опытно-конструкторская работа №10 по созданию ультрабыстродействующего модуля аналого-цифрового преобразователя с большим динамическим диапазоном.
# Краткая характеристика:
Разработка внешнего модуля аналого-цифрового преобразователя DSP160x1-1220 с максимальной частотой дискретизации до 2ГГц и с разрешением АЦП 12 бит. Данный модуль позволит обеспечить мгновенный реальный динамический диапазон SFDR 63-65 дБ (1778 раз) в одновременной частотной полосе до 1000 МГц. Предварительная быстродействующая цифровая обработка сигнала (ЦОС), реализованная на ПЛИС типа XC4VLX160 или XC5V позволит обеспечить входную скорость данных в реальном масштабе времени. Возможность дополнительной обработки сигнала с помощью встроенного сигнального процессора типа TMS320C6415 (опционально). Габариты модуля 190х260х60, принудительная вентиляция, компьютерный интерфейс USB2.0.
# Основные задачи решаемые создаваемым оборудованием:
* Построение панорамных мониторинговых систем широкополосных сигналов. * Построение радиотехнических систем с ПЧ до 1750 МГц и полосой одновременной обработки до 500 МГц. * Многоканальные измерения и регистрация высокочастотных сигналов. * Регистрация и обработка сигналов в реальном времени в большом динамическом диапазоне. * Регистрация сигнала с высокой скоростью нарастания амплитуды по 1700 каналам.
# Экономические показатели:
* Срок реализации проекта 11 месяцев * Планируемая рыночная стоимость OEM модуля - 1 299 000 рублей c 18% НДС * Необходимый объем финансирования 19.5 млн. рублей
Первые результаты ОКР №10
Появились первые результаты выполнения ОКР №10 разработки и создании ультрабыстродействующего модуля АЦП.
Назначение. (Предварительные данные)
Внешний модуль быстродействующего АЦП DSP55x1-1220 предназначен для работы с широкополосными сигналами. Уникальное сочетание одновременно широкой обрабатываемой полосы до 1ГГц и высокого разрешения АЦП 12 бит позволяет данному модулю работать в качестве спектроанализатора и осуществлять режим панорамного мониторинга.
Отличительные характеристики:
* Максимальная частота дискретизации до 2.5 ГГц; * Разрешение АЦП - 12 бит; * SFDR 80 дБ(FS).
Отправлено: 29.10.10 11:40. Заголовок: ГЛАВА 3 АНАЛОГО-ЦИФР..
ГЛАВА 2 ДИСКРЕТНЫЕ СИСТЕМЫ Дискретизация аналоговых сигналов по времени Статические передаточные функции АЦП и ЦАП и погрешности по постоянному току Погрешности по переменному току в тракте преобразователя данных Динамические характеристики ЦАП 1
Отправлено: 30.10.10 17:18. Заголовок: This is a real-life ..
This is a real-life example of the signal processing involved with a typical monopulse radar application. As shown in Figure 3, the system uses a multi-element antenna where the received signals consist of three types: Azimuth, Elevation and the sum of these two. The signals to be digitized and processed are as follows:
Azimuth difference or ΔA which is equal to A1 – A2 Elevation difference or ΔE which is equal to E1 – E2 Sum Channel Σ which is equal to the sum of A1 + A2 + E1 + E2 The phase shift between Σ and ΔE determines the elevation of the target The phase shift between Σ and ΔA determines the azimuth of the target The IF center frequency of these signals is 140 MHz and the IF bandwidth is 40 MHz This signal processing requires three channels of A/D converters
Let’s assume that we want to track aircraft targets between a distance of 15 km and 45 km from the radar location. Radar signals travel at the speed of light which is equal to 300,000 km/sec.
For targets at 15 km, the round trip for the radar pulse takes 2 x 15 km ÷ 300,000 km/sec = 100 μsec. For targets at 45 km, the round trip takes 2 x 45 ÷ 300,000 km/sec = 300 μsec. Figure 4 shows the timing required to collect the data. Generate a 50 μsec pulse at T0; start collecting data at T = T0 + 100 μsec; stop collecting data at T = T0 + 300 μsec.
As shown in Figure 9, we chose the complex baseband signal to have 40 MHz bandwidth. When translated to the 140 MHz IF, the 40 MHz signal extends from 120 MHz to 160 MHz. ######################################## The output sampling frequency must be at least twice the 160 MHz highest frequency, or 320 MHz minimum. Let’s choose 400 MHz to be on the safe side, and use the interpolation filter and DUC to translate the baseband to the IF frequency.
Summary The Pentek Model 71621 Transceiver XMC module is a complete radar signal generation, timing and acquisition subsystem. It has the three A/Ds required for monopulse radar and standard on-board support for signal generation and acquisition timing.
Radar data acquisition is facilitated by the 200 MHz, 16-bit A/Ds which capture the 140 MHz IF signals with 40 MHz ########################################################################
140 mgz centr PCH ,40 mgz polosa ot 120 mgz do 160 mgz -----------------------------------------------------------------------
bandwidth. Wideband DDC IP cores convert the IF signals down to baseband. The A/D input controller engine uses a simple parameter table that creates programmable delays, acquisition record lengths and complex acquisition scenarios.
Radar waveform generation uses a D/A controller engine with a simple parameter table. It creates multiple waveforms with programmable delays and lengths. The wideband DUC upconverts the digital baseband waveform to 140 MHz IF and the 400 MHz, 16-bit D/A delivers 140 MHz IF signal with 40 MHz bandwidth.
Отправлено: 30.10.10 17:57. Заголовок: In the words of a us..
In the words of a user, Robert Sgandurra, Senior Product Manager with modular DSP and SDR developer Pentek (www.pentek.com), “TI continues to push the performance envelope with high-speed ADCs. The ADS5485 was a clear choice for our model 7150 Quad A/D Software Radio Module. The higher sample rate means that users will be able to directly digitize nearly 100 MHz of bandwidth, which is invaluable for our customers working on wideband radar and wideband communication systems.”
Отправлено: 30.10.10 21:19. Заголовок: DAnnie po dinamiches..
DAnnie po dinamicheskomu diapazonu woennogo radara USA
The AN/TPS-75 Radar System [ "Tipsy 75"] is a mobile, tactical radar system capable of providing radar azimuth, range, height, and Identification Friend or Foe (IFF) information for a 240-nautical-mile area. This deployable/transportable radar system is capable of providing long range radar data to support operations and control of tactical aircraft. The TPS-75 today forms the backbone of the US Air Force Air Defense system. The AN/TPS-75 Radar system provides a "real-time" radar airspace picture and data in support of the battle commander and the Ground Theater Air Control System (GTACS) via radio, telephone, microwave relay, or satellite communications link. The AN/TPS-75 radar system includes the UPX-27 IFF/SIF equipment, Tactical Air Operation Interface Gp OA 9194/TYQ-23(V)2, Modular Control Equipment Interface Group (MIG) and AN/TLQ-32 ARM Decoy. The AN/TPS-75 is a mobile ground radar set designed to conduct long-range search and altitude-finding operations simultaneously
Weight shelter - app. 8,400 pounds antenna - app. 7,400 pounds Pulse Repetition Frequency (PRF) 235, 250, 275 +/- 0.5 Hz fixed, and two selectable average PRFs; 250 and 275 staggered. For each staggered selection, the transmitter operates sequentially on one of seven PRFs. Transmitter Characteristics peak power - 2.8 MW nominal verage power - 4.7 kW nominal pulse width - 6.8 +/- 0.25 microseconds
Receiver Characteristics type -seven logarithmic channels sensitivity - negative 105 dB mds dynamic range - 70 dB search, 70 dB height intermediate frequency - 32 MHz 3-D Coverage (Search, Height and Range) azimuth - 360 degrees (operator controlled blanking optional) elevation angles - 0.5 to 20 degrees above the radar horizon maximum altitude - 95,500 feet range - one to 240 nautical miles scanning rate - approximately 6.5 rpm
dimensions 11 feet high by 18 feet 4 inches wide polarization vertical beam width - 1.1 degrees horizontal and 1.55 degrees to 8.1 degrees with a total of 20 degrees (6 stacked beams)
------------
dynamic range - 70 dB search, 70 dB height
dinamicheskij diapazon sowremennix 16 bit ADC wische ... ************************************************* + NLEQ /nelinejnij equaliser iz Lincoln laboratory 12-24 db ...
Отправлено: 31.10.10 19:49. Заголовок: Dannie 16 bit ADC ..
Dannie 16 bit ADC k 140 mgz centr PCH ,40 mgz polosa ot 120 mgz do 160 mgz -----------------------------------------------------------------------
ADS5485 TI 200 msps AD9467 250 msps SNR 130 mgz -74.8 db n/d 140 mgz - n/d 74.4/76 db 170 mgz -74.8 db 74.3db/75.8db SFDR 130 mgz -85 db n/d 140 mgz -n/d 94/95 db 170 mgz -78 db 93/92 db SINAD 130 mgz -72.9db n/d 140 mgz n/d 74.4/76 db 170 mgz -71.7 db 74.2db/75.8db Price -125$ AD9467 po dinamicheskomu diapazonu lutsche - dlja primera pentek 92 db + wiigrisch ot NLEQ Lincoln laboratory 12 db = 104 db
Xoroscho --------
----------------------------------------- Summary The Pentek Model 71621 Transceiver XMC module is a complete radar signal generation, timing and acquisition subsystem. It has the three A/Ds required for monopulse radar and standard on-board support for signal generation and acquisition timing.
Radar data acquisition is facilitated by the 200 MHz, 16-bit A/Ds which capture the 140 MHz IF signals with 40 MHz ########################################################################
140 mgz centr PCH ,40 mgz polosa ot 120 mgz do 160 mgz -----------------------------------------------------------------------
bandwidth. Wideband DDC IP cores convert the IF signals down to baseband. The A/D input controller engine uses a simple parameter table that creates programmable delays, acquisition record lengths and complex acquisition scenarios.
Radar waveform generation uses a D/A controller engine with a simple parameter table. It creates multiple waveforms with programmable delays and lengths. The wideband DUC upconverts the digital baseband waveform to 140 MHz IF and the 400 MHz, 16-bit D/A delivers 140 MHz IF signal with 40 MHz bandwidth.
Отправлено: 31.10.10 20:21. Заголовок: THEORY OF OPERATION ..
THEORY OF OPERATION The AD9467 architecture consists of an input-buffered pipe-lined ADC that consists of a 3-bit first stage, a 4-bit second stage, followed by four 3-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The input buffer provides a linear high input impedance (for ease of drive) and reduces the kick-back from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers.
Отправлено: 01.11.10 14:15. Заголовок: The V-Corp proprieta..
The V-Corp proprietary LinComp approach requires less hardware than phase-plane compensation and provides up to 24 dB or more reduction in harmonic distortion, does not require slope estimates, and is capable of super-Nyquist error compensation (i.e., direct synthesis of high IF data).
Отправлено: 01.11.10 16:04. Заголовок: A 5 Gsps 8-10 bit AD..
A 5 Gsps 8-10 bit ADC Platform Concept for RF and Instrumentation Applications François BORE, e2v, avenue de Rochepleine, BP123, 38521 Saint-Egrève Cedex, France www.e2v.com
Отправлено: 01.11.10 19:28. Заголовок: Adding the HMC660LC..
Adding the HMC660LC4B Track-and-Hold Amplifier to a lower bandwidth ADC allows the ADC to subsample a fairly broadband signal (for example, 1 GHz centered at 3.5 GHz) and then directly convert (or alias) it to baseband frequency for conversion by a lower-speed, high-resolution ADC.
When used with lower sample rate converters, the HMC660LC4B can provide an extension of input sampling bandwidth. When used with higher sample rate converters, the THA can provide improved high frequency linearity. For example, the linearity of even the highest speed, state-of-the-art AT84AS008 Atmel converter starts to significantly degrade above 2 GHz, and linearity is not specified above this frequency, even though the device supports an input bandwidth of 3.3 GHz. Since the full-scale input for this converter is 0.5 Vpp, the HMC660LC4B would operate at half-full-scale in this application (SFDR ~60 dB or better over the input band) and could provide both a bandwidth extension to 4.5 GHz, as well as improved high frequency linearity when used with this type of converter.
Отправлено: 01.11.10 22:22. Заголовок: Military and space ..
Military and space
The military and space industries tend to favor high-speed ADCs reaching high-sampling frequencies beyond GSPS, using a single-core architecture and no hidden internal interleaving. -------------------------------------
It is known that interleaving ADC cores in systems that are subject to wide temperature swings requires temperature monitoring and management of calibration and re-calibration each time the system is subject to significant temperature changes (see Ref 1). Therefore, data converters that achieve GSPS sampling rates with a single high-speed core and thus without using any interleaving techniques show nominal performance across their full temperature range without having to manage calibrations and without using FPGA processing power to remove interleaving spurs in the digital domain.
The contract awarded by the European Space Agency to e2v technologies to develop a 10-bit 1.5 GSPS (see Ref 2) will result in a data converter specifically designed to meet the requirements of the space industry and will indeed reach 1.5 GSPS without any internal interleaving and still meet low-power requirements.
The military industry welcomes both high-input frequencies and high-sampling rates without internal interleaving for the same reasons of performance across temperature range explained above. They are users of devices such AT84AS004, EV10AS150 and similar devices.
The GSPS data conversion industry is an area where CMOS and bipolar technologies still compete to some extent. The recent designs from e2v on both Infineon B7HF200 full bipolar process and Jazz Semiconductor high-speed BiCMOS processes achieve power consumption levels that are comparable to CMOS GSPS data converters, but with higher input bandwidths typical of fast bipolar technologies. Reduced supply current transients — such as with e2v’s EV10AQ190 and ADC cores — which can sample signals as fast as 2.5 GSPS without the use of any form of internal interleaving (such as e2v’s EV10AS150). On the other side, CMOS devices typically have a power consumption that is proportional to the sampling frequency and thus the nominal power consumption is reduced in applications where the ADC clock can be slowed down.
10-bit GSPS ADC-overview
10-bit GSPS ADC Typical Power consumption overview. Source: Suppliers datasheets published on their respective Web sites.
10-bit ADCs:
• EV10AQ190 Quad 10-bit 1.25-GSPS device from e2v technologies. BiCMOS process technology from Jazz Semiconductor; power consumption per channel sampling at 1.25 GSPS: 1.4 W /channel at 1.25 GSPS.
• ADC10D1000 dual 10-bit 1-GSPS ADC from National Semiconductor. Supplier’s own CMOS Process technology; power consumption per channel sampling at 1 GSPS: 2.77 W in total for 2 channels enabled or 1.61 W for single channel enabled.
For the foreseeable future, the choice of standard GSPS ADCs will continue to increase with a combination of additional integrated features, higher sampling rates and higher input bandwidths accommodating input signals frequencies well into the S-Band.
Отправлено: 02.11.10 19:24. Заголовок: New Products 10bit 2..
New Products 10bit 2.5Gs/s ADCs for high RF sampling applications October 16, 2009 | | 220601094 e2v, has announced production of a 10bit 2.5Gs/s analog to digital converter (ADC) incorporating 5GHz analog input bandwidth for operation over the L-band and S-band frequencies. Chelmsford, UK - e2v, has announced production of a 10bit 2.5Gs/s analog to digital converter (ADC) incorporating 5GHz analog input bandwidth for operation over the L-band and S-band frequencies. The EV10AS150ATP ADC is being exhibited at the International Radar Conference, RADAR'09 in Bordeaux, France.
This device's high sampling rate of 2.5Gs/s suits it to applications such as high speed test instrumentation, automatic test equipment (ATE), high speed data storage, software defined radio, radar and flight simulators and wideband satellite receivers. The company points out that the device will enable designers to process 1GHz of IF analogue signal, without needing multiple down-conversion stages.
The EV10AS150ATP series – the first in a family of pin-compatible 10bit ADCs – boasts a spurious free dynamic performance of 60dB and 52dB signal to noise ratio (SNR). According to e2v, IMD3 is 60dBc, whilst it's effective number of bits (ENOB) is 8.1bits. The EV10AS150ATP, which comes in a EBGA 317 pin package (25 x 35mm) is made using Infineon's high-speed bipolar SiGe silicon technology, with both commercial and industrial grade versions now available.
Отправлено: 03.11.10 00:26. Заголовок: IF undersampling Th..
IF undersampling
The IF undersampling technique has long been sought as a means for reducing the complexity of a receiver design. In fact, sampling as close to the antenna as possible offers the possibility of reducing the size and complexity of the receiver function in a system. Most modern cellular base stations implement IF sampling allowing one or more IF stages to be eliminated from their system reducing both cost and complexity.
While IF undersampling does reduce overall system cost, there is a performance trade off in that IF undersampling ADCs in the past have generally resulted in lower performance than baseband sampling ADCs. #########################################################
Over the past few years, this requirement has driven the demand for high-performance IF sampling ADCs and are now available that are optimized for SNR and SFDR for frequencies as high as 450 MHz.
Sample rates are driven by several factors. The largest driver is to have a sample rate that is an integer multiple of common data rates for communication standards. For example, CDMA2000 has a base symbol rate of 1.2288 MHz, WCDMA has a base rate of 3.84 MHz and TD-SCDMA has a base rate of 1.28 MHz. Based on these rates, common sample rates of 78.6, 92.16, 122.88 and 245.76 megasamples per second (Msps) are common. As in the past, the ADC technology determines the preferred sample rate. And over the past few years, the preference is to run above 80 Msps in most new designs.
Higher sample rates do improve noise performance of ADCs. While the overall integrated noise does not improve, the distribution of the noise over wider bandwidths does offer improvements in noise spectral density (NSD). The lower the noise spectral density, the more sensitive a receiver can be designed. This process is often referred to as processing gain and is nothing more than distributing the same noise over a wider band of frequencies and then digitally filtering out the noise in the frequency bands that are not of interest. Doubling the sample rate can improve the noise spectral density by a factor of 3 dB resulting in a significant improvement in performance of many systems.
However, there are limits to how much sample rates can be increased. Current FPGA[1] and ASIC[1] technology limits CMOS[1] data rates to about 250 MHz, LVDS[1] to approximately 800 MHz and PECL[1] to approximately 1.5 GHz. Other logic schemes such as CML[1] offer the possibility of even higher rates. While some applications have moved to LVDS and PECL, the bulk of applications are implemented in CMOS. This will change in the future, but for now, the mainstream driving applications are still CMOS.
A High Dynamic Range Receiver for the Radar **************************************** Open System Architecture
2008
X-Band Receiver The MITEQ X-Band receiver is of a dual conversion superheterodyne architecture that translates a 10 GHz signal with a bandwidth of 1 GHz to an IF center frequency of 70 MHz and a bandwidth of 20 MHz for stretch processing of radar returns. The receiver also includes a wideband IF output at 1 GHz for use with advanced high speed ADC (analog to digital converter) processing techniques such as optical processing, time sequenced ADC arrays, or time stretched ADC arrays
High-Dynamic-Range Receivers for Digital Beam Forming Radar Systems Keir C. Lauritzen, Joseph E. Sluz, Matthew E. Gerwell, Albert K. Wu, and Salvador H. Talisa, The Johns Hopkins University Applied Physics Laboratory, 11100 Johns Hopkins Road Laurel, MD 20723
Отправлено: 04.11.10 00:36. Заголовок: ABOUT GMR office GM..
ABOUT GMR office GMR Research & Technology in Acton, MA.
GMR Research & Technology is a small, privately owned company located in Concord, Massachusetts and Acton, Massachusetts. Founded in March 2004 by Dr. Gil M. Raz, GMR is developing innovative nonlinear signal processing techniques to improve high-speed communications and surveillance systems.
An example of the GMR innovations includes a proprietary method for parsimoniously achieving several orders of magnitude measured improvement in linear dynamic range for very wideband RF sensors. This method requires no changes in the analog front-end of the sensor system and is performed entirely in the digital domain after sampling. These results were achieved in collaboration with MIT - Lincoln Laboratory. This technology is currently funded to be inserted into sensor system platforms built at the Northrop Grumman Corporation. -----------------------------------------------------------------------------------------------------------
GMR is actively developing and securing intellectual property for solving problems difficult or intractable for traditional signal processing. GMR has several patents pending including one for its Non-Linear Affine Transform technique (NoLAff). http://gmrtech.com/about.html<\/u><\/a>
Отправлено: 04.11.10 19:24. Заголовок: There are also other..
There are also other advantages gained by increasing sampling frequency. Over-sampling signals also enables processing-gain benefits in the digital domain with the use of digital filtering. This is because the ADC noise floor can be spread over a larger output bandwidth. Doubling the sampling rate, for a fixed input bandwidth, results in a 3 dB improvement in dynamic range. Every further doubling of the sampling frequency provides an additional 3 dB of dynamic range
radioljubitelskaja tochka zrenija na dinamicheskij diapazon ...
toze polezna ,kak i rekord na 10 ghz s 10 watt 90 santimetrow diametrom antennoj -2000 km
Conclusions When using the concept of dynamic range in Amateur Radio, we should refer to signals present simulta- neously at the antenna input. This means that BDR — implying that blocking means that the ability to copy the desired signal as blocked by a strong off-channel signal — for the FT-1000D is 96.5 dB. When the de- sired signal is placed at –77 dBm (see Note 2), the point of saturation, which was +20 dBm in QST (see Note 3) has to be compared to –77 dBm for a dy- namic range of 97 dB, ----------------------------------------
not to the MDS value measured under quite different circumstances. The value of 150 dB reported in QST is not the dynamic range for two simultaneously present signals. -------------------------------------------
It is the dynamic range for a single signal and is not of much inter- est to a radio amateur.
Отправлено: 04.11.10 22:49. Заголовок: By 1972, fabrication..
Radar Signal Processing Robert J. Purdy, Peter E. Blankenship, Charles Edward Muehe, Charles M. Rader, Ernest Stern, and Richard C. Williamson s This article recounts the development of radar signal processing at Lincoln Laboratory. The Laboratory’s significant efforts in this field were initially driven by the need to provide detected and processed signals for air and ballistic missile defense systems. The first processing work was on the Semi-Automatic Ground Environment (SAGE) air-defense system, which led to algorithms and techniques for detection of aircraft in the presence of clutter. This work was quickly followed by processing efforts in ballistic missile defense, first in surface-acoustic-wave technology, in concurrence with the initiation of radar measurements at the Kwajalein Missile Range, and then by exploitation of the newly evolving technology of digital signal processing, which led to important contributions for ballistic missile defense and Federal Aviation Administration applications.
By 1972, fabrication of the first reflective-array compressor (RAC) was initiated; this device is illustrated in Fig- ure 2. The first RAC device was a linear-FM filter with a 50-MHz bandwidth (on a 200-MHz carrier) matched to a 30-μsec-long waveform [16–18]. This arrangement yielded a time-bandwidth product of 1500, more than an order of magnitude greater than that achieved by interdigital-electrode SAW devices [19]. The response was remarkably precise; the phase deviation from an ideal linear-FM response was only about 3° root mean square (rms). Pairs of matched RACs were used in pulse-compression tests in which the first device functioned as a pulse expander and the second as a pulse compressor. The compressed pulsewidths and sidelobe levels were near ideal. Armed with these encouraging results, researchers took the next step by developing RAC devices for spe- cific Lincoln Laboratory radars. RAC Pulse Compressors for the ALCOR Radar The ARPA-Lincoln C-band Observables Radar, or ALCOR [20], on Roi-Namur, Kwajalein Atoll, Mar- shall Islands, had a wideband (512 MHz) 10-μsec- long linear-FM transmitted-pulse waveform (see the article entitled “Wideband Radar for Ballistic Missile Defense and Range-Doppler Imaging of Satellites,” by William W. Camp et al., in this issue). ALCOR was a key tool in developing discrimination tech- niques for ballistic missile defense. The wide band- width yielded a range resolution that could resolve in- dividual scatterers on reentering warhead-like objects. This waveform was normally processed with the STRETCH technique, which is a clever time-band- width exchange process developed by the Airborne Instrument Laboratory [21, 22]. The return signal is mixed with a linear-FM chirp and the low-frequency sideband is Fourier transformed to yield range infor- mation. For a variety of reasons, the output band- width and consequently the range window were lim- ited. For example, the ALCOR STRETCH processor yielded only a thirty-meter data window. Therefore, examination of a number of reentry objects, or the long ionized trails or wakes behind some objects, re- quired a sequence of transmissions. This sequential approach was inadequate in deal- ing with the challenging discrimination tasks posed by reentry complexes, which consist not only of the reentry vehicle, but also a large number of other ob- jects, including tank debris and decoys, spread out over an extended range interval. What was needed was a signal processor capable of performing pulse compression over a large range interval on each pulse. Lincoln Laboratory contracted with Hazeltine Labo- ratory to develop a 512-MHz-bandwidth all-range analog pulse compressor employing thirty-two paral- lel narrowband dispersive bridged-T networks built
During 1972 and 1973, Lincoln Laboratory devel- oped a 512-MHz-bandwidth (on a 1-GHz interme- diate frequency [IF]) 10-μsec RAC linear-FM pulse compressor [23]. #############
A trimming technique was developed to achieve an adequately precise response. This tech- nique required measuring the device and the subse- quent deposition of a corrective metal pattern of vary- ing width on the crystal surface of the RAC, as illustrated in Figure 2. The resulting precision al- lowed for a phase response that was precise to about 2.5° rms, or about one part per million over the 5120 cycles of the waveform. This response yielded near-in- range sidelobes in the –35-dB range, whereas far-out sidelobes rapidly fell to better than 40 to 50 dB down, as shown in Figure 4. In Figure 5, which is a photo- graph of a RAC developed for ALCOR, the two rain- bow-colored stripes near the centerline of the crystal show light that is diffracted from the etched grating. The phase-compensating varying-width metal film strip runs down the centerline of the crystal. Pairs of approximately one-inch-long matched RAC devices were installed in ALCOR in 1974 and were used successfully in a series of reentry tests. These devices proved to be such powerful wide-band- width signal processors that advances in analog-to- digital converter technology to capture the output were required before the capability of the RAC de- vices could be fully utilized.
Отправлено: 04.11.10 23:05. Заголовок: Nulling Over E..
Nulling Over Extremely Wide Bandwidths When Using Stretch Processing Richard M. Davis Jose A. Torres J. David R. Kramer Ronald L. Fante The MITRE Corporation 202 Burlington Road, Bedford, MA, 01730-1420 rmdavis@mitre.org, torres@mitre.org, dkramer@mitre.org, rfante@mitre.org Adaptive Sensor Array Processing Workshop March 10-11, 1999 15121501 4/6/99 2 Outline 0 The Problem 0 Traditional Solutions 0 A New Approach 0 Numerical Results 0 Summary MITRE 4/6/99 3 The Problem 0 Given radar capable of radiating extremely wideband waveforms (100 -1000 MHz) 0 Desire protect radar against sidelobe noise jamming 0 Each frequency within jammer’s spectrum is received with different sidelobe gain. 0 Number of sidelobes jammer spreads through equals time-bandwidth product (TB) TB = D(sinθ - sinθο)B/C where T = Difference in arrival time of plane wave across array face B = Jammer bandwidth D = Array diameter θο = Time-delay steered beam pointing direction
Отправлено: 04.11.10 23:49. Заголовок: n the classic sense,..
n the classic sense, analog receiver system design employs cascade linearity (second and third-order intermodulation) and noise figure calculations based on individual component characteristics. We desire to use the same analysis for a proposed SAR receiver, which may employ a THA for direct 4 GHz IF sampling. Hence, we needed to first characterize component-level parameters such as the 1 dB gain compression, the output third-order intercept (TOI), signal-to-noise ratio (SNR), spurious-free dynamic-range (SFDR), and noise figure (NF) for the THA. In addition, time-domain jitter or phase noise degradation of the THA must be quantified to understand its potential impact to the Doppler-domain dynamic range performance of the SAR. The purpose of this report is to document the above mentioned measurements performed on the Rockwell Scientific RTH010 [2] THA, which has been identified as a prime candidate, and possibly the only currently available candidate THA for our application. All measurement parameters and configurations are catered specifically to the direct IF sampling application mentioned. The measured data was then analyzed (some quantitative, some qualitative) to determine the general impact of the non-idealities of the THA to SAR performance.
Figure 2: Comparison of simplified block diagrams for the current SAR IF configuration and the proposed digital IF implementation employing a fast THA. The “Old Way” shows the current implementation. Currently, analog down-conversion, analog IF filtering using surface-acoustic wave (SAW) filters, and analog quadrature (I/Q) demodulation are employed. The “Digital Way” performs the necessary frequency conversion by direct sampling the IF using the THA and the ADC. IF filtering and quadrature demodulation, amongst other DSP operations, are all performed in FPGAs. We are currently developing a digital IF receiver module upgrade to our current SAR. This module utilizes bandwidth over-sampling and high-throughput DSP functions in FPGAs. However, we have chosen not to employ a THA to direct sample the IF. Instead, classic analog down-conversion is employed due to it’s lower implementation risk. Future radars developed at Sandia National Labs may very well employ the benefits of direct sampling using a THA, assuming that the device meets the system performance requirements.
Analog Bandwidth The THA must certainly support the 4 GHz direct IF sampling application. In addition, we wish to measure the gain of the THA vs. frequency to assess the possibility of using the RTH010 for future direct sampling applications up to X-band frequencies.
Noise Figure The noise figure performance of the THA at 4 GHz helps determine the lower limit of the SAR dynamic range. SFDR and SNR Both SFDR and SNR are measured and compared to the same parameters for the ADC itself. Since the ADC is typically the dynamic range “bottleneck” in a SAR employing stretch processing, we want to carefully assess the effective number of bits (ENOB) of the THA and ADC as compared to the ADC alone.
4.1.4 Analog Bandwidth and Input/Output Impedance We found that the output response was not very flat over the band of DC to 7GHz when measured in the continuous-time domain. Therefore we were prompted to look at the input and output impedance of the THA and the input impedance of the 180° hybrid coupler. We found that this variation in the output response was due primarily to the impedance variation of the hybrid coupler (or balun) and the THA: • The input impedance of the THA varies from 51.85 (at 500 MHz) to 37.96 (at 4 GHz) to 74.50 (at 6 GHz) ohms. • The output impedance of the THA varies from 34.76 (at 50 MHz) to 54.94 (at 450 MHz) ohms. • The input impedance of the 180° hybrid coupler varies from 48.47 (at 50 MHz) to 100.10 (at 450 MHz) ohms. • We also tried a balun on the THA output in place of the 180° hybrid coupler. The results were similar, due to the input impedance of the balun varying from 23.23 (at 50 MHz) to 69.37 (at 400 MHz) to 53.24 (at 500 MHz) ohms.
The primary components utilized in the discrete-time measurements are the ADC (Maxim MAX108) operating nominally at 1 GHz, the FPGA (Xilinx XC2V1000), and the VME interface. For each ADC vector acquisition, data is stored in RAM located in the FPGA, then transferred to a Motorola 2307 processor via the VME interface. From there, the data is accumulated (if necessary), then transferred to a PC running Matlab via an ethernet link.
10 bit e2v 2.5 gsps,8 bit ENOB,60 db SFDR awtoru ponrawilsja bolsche chem max108 i 109 (oba 8-bitnie ) w 2002 ego ne bilo ...
Отправлено: 05.11.10 00:21. Заголовок: x band radar s polo..
x band radar s polosoj 1 ghz ,razrescheniem 150 mm ,ispolzuetsja atmel 10 bit 2.2 gsps ( teper eto e2v)
High resolution range-Doppler radar demonstrator based on a commercially available FPGA card”, proceedings Radar 2008, Adelaide, Australia. pdf
An X-band high resolution range-Doppler radar demonstrator has been developed, based on a commercially available 6U-VXS form-factor digital signal processing card containing all necessary base-band circuitry. The custom design covers a radio frequency up-down converter, FPGA firmware and PC software. The practical signal bandwidth is close to 1GHz and the range resolution is close to 15cm. The functionality has been demonstrated in a free space radiation experiment.
By: Henning Nicolaisen#1, Tor Holmboe*2, Karina Vieira Hoel*3, Stein Kristoffersen*4 #University of Oslo, Department of Informatics P.O. Box 1080 Blindern, NO-0316 Oslo, Norway * Norwegian Defence Research Establishment
The radar resolution in range and Doppler can be varied within wide limits, from the resolution typical of air target range-Doppler radars to the high resolution representative of ynthetic aperture radars (SAR) and inverse SAR (ISAR) systems. However, no radar trajectory compensation, antenna steering or target following function is implemented and the MuPuRF radar mode does not represent an operational system in this respect. The Nyquist digital signal bandwidth of MuPuRF is 1 GHz, corresponding to 15 cm theoretical range resolution. he TRITON VXS-1, produced by Tekmicro [2], is a single-slot 6U form factor card and is in accordance with the VITA 41.0 VXS specification. The advertised key applications for the TRITON VXS-1 include radar, electronic warfare, software radio and telecommunications. Figure 2 shows the main components and signal paths. The core of the TRITON VXS-1 is a Xilinx Virtex-II Pro FPGA circuit along with a 10bit ADC and a 12bit DAC. Both converters can operate at 2 GSamples/sec, giving a Nyquist digital signal bandwidth of 1 GHz. The analog 3 dB-bandwidth extends from 3 MHz to 3 GHz.
Отправлено: 05.11.10 00:43. Заголовок: Fast Facts: Founded..
Fast Facts: Founded: November 1981 Employees: 35 Privately Held ISO 9001 Certified
The QuiXilica V5 Architecture provides a simple flexible parallel interface that enables boards to be factory configured with different ADCs and DACs, thus enabling the boards to meet a robust variety of applications. High bandwidth support for ADCs and DACs operating beyond 5 GSPS is designed into the architecture.
Front-end/Back-end XMC Architecture: Unique two-part XMC design separates the protocol interface (front-end) from the standard back-end interface (PMC, XMC) and provides powerful advantages at many levels for customers who need to integrate, maintain, or upgrade multiple I/O modules. New protocol interfaces can quickly be added to existing back-ends as technology becomes available. Protocol interfaces can be upgraded with new back-end interfaces as technology demands.
Representative Customers Alenia Marconi Systems BAE General Dynamics L-3 Communications Lockheed Martin MIT NASA Northrop Grumman Raytheon Recon Optical Inc. Rockwell Collins
Отправлено: 05.11.10 02:27. Заголовок: The AN/FPS-16 is a h..
The AN/FPS-16 is a highly accurate ground-based monopulse single object tracking radar (SOTR), used extensively by the NASA manned space program and the U.S. Air Force. The accuracy of Radar Set AN/FPS-16 is such that the position data obtained from point-source targets has azimuth and elevation angular errors of less than 0.1 milliradian (approximately 0.006 degree) and range errors of less than 5 yards (5 m) with a signal-to-noise ratio of 20 decibels or greater.
s antennoj 3.9 metra , IF /Pch -30 mgz i polosoj 8 mgz ######################################
The sum, azimuth, and elevation signals are converted to 30 MHz IF signals and amplified. The phases of the elevation and azimuth signals are then compared with the sum signal to determine error polarity. These errors are detected, commutated, amplified, and used to control the antenna-positioning servos. A part of the reference signal is detected and used as a video range tracking signal and as the video scope display. A highly precise antenna mount is required to maintain the accuracy of the angle system.
t..e ne wse rezimi raboti RLS trebujut polosi 500 mgz-8000 mgz kak SAR/ISAR ,kotorie mogut razlichat yabch ot loznoj celi po kinematike dwizenija #################################################################################################
IF/PCH 30 mgz ,polosa 8 mgz -eto 16 bit AZP ... s dither , NLEQ processor eto okolo 110 db dinamicheskij diapazon
s kombinaziej drugix metodow wozmozno bolsche
podxodjat rjad AZP AD9467 250 msps/16 bit ,TI ADS5485 16 bit/200 msps ,LTC2209 160 msps/16 bit
Отправлено: 05.11.10 02:47. Заголовок: Some notes on the AN..
Some notes on the AN-FPQ 6 Radar
The AN-FPQ 6 radar was built by RCA and was, effectively, a development of the AN-FPS 16. The Q6, as it was known by those who worked on it, was an amplitude comparison monopulse C-band radar, with a 2.8 MW peak klystron transmitter tunable from 5.4 to 5.8 GHZ, which had a 9 meter parabolic antenna, having 52 dB gain, a 0.6 degree beam width, utilizing a Cassegrainian feed with a five horn monopulse comparator. This radar had an unambiguous maximum range of 215 or 32,768 nautical miles (60,686 km), and employed uncooled parametric amplifiers with a system noise temperature of 440 K, [a noise figure of 4 dB].
A major features of the radar was its maximum unambiguous range of 32,768 nautical miles (60,686 km) despite a pulse repetition frequency [PRF]of some hundreds of pulses per second.
RCA’s Missile and Surface Radar Division developed the FPQ-6 skin tracking C-Band radar as a successor to the AN/FPS-16 radar set. The AN/FPQ-6 can provide continuous spherical coordinate information at ranges of 32,000 nautical miles (59,000 kilometers) with an accuracy of plus and minus 6 ft (1.8 m). The AN/FPS-16 has range limited to 500 nmi (930 kilometers) with an accuracy of 15 feet (5 m), although it could be modified to a maximum range of 5,000 nmi (9,300 kilometers).
mit/receive circuit. The transmit side includes phase control and field-effect transistor (FET) power amplification at 17 GHz, and a frequency doubler. On the receive side, a dual unit incorporates a transmit/receive switch and a mixer that produces the intermediate frequency (IF) at 1 to 2 GHz. This dual
driving a doubler to produce output power at 34 GHz [72]
Gallium-ars- enide MMIC transmit/receive-module technology is used in the X-band (8.0 to 12.0 GHz) theater-mis- sile-defense phased-array radar system [54] built by Raytheon Corporation.
THAAD IF ?
The measured average sidelobe level is –50 dB, close to the theoretical value. Space-based radars or airborne radars can use multiple displaced phase centers to cancel clutter, as described in the ar- ticle by Muehe and Labitt in this issue. A
The Development of Phased-Array Radar Technology Alan J. Fenn, Donald H. Temme, William P. Delaney, and William E. Courtney Lincoln Laboratory has been involved in the development of phased-array radar technology since the late 1950s. Radar research activities have included theoretical analysis, application studies, hardware design, device fabrication, and system testing. Early phased-array research was centered on improving the national capability in phased-array radars. The Laboratory has developed several test-bed phased arrays, which have been used to demonstrate and evaluate components, beamforming techniques, calibration, and testing methodologies. The Laboratory has also contributed significantly in the area of phased-array antenna radiating elements, phase-shifter technology, solid-state transmit-and- receive modules, and monolithic microwave integrated circuit (MMIC) technology. A number of developmental phased-array radar systems have resulted from this research, as discussed in other articles in this issue. A wide variety of processing techniques and system components have also been developed. This article provides an overview of more than forty years of this phased-array radar research activity.
Отправлено: 05.11.10 03:15. Заголовок: ALCOR operates at C..
ALCOR operates at C-band (5672 MHz) with a signal bandwidth of 512 MHz that yields a range resolution of 0.5 m. (The ALCOR signal was heavily weighted to produce low range sidelobes with the concurrent broadening of the resolution.) Its wide- bandwidth waveform is a 10-μsec pulse linearly swept over the 512-MHz frequency range. High signal-to- noise ratio of 23 dB per pulse on a one-square-meter target at a range of a thousand kilometers is achieved with a high-power transmitter (3 MW peak and 6 kW average) and a forty-foot-diameter antenna. Cross-range resolution comparable to range resolu- tion is achievable with Doppler processing for targets rotating at least 3° in the observation time. The pulse- repetition frequency of this waveform is two hundred pulses per second
Processing 500-MHz-bandwidth signals in some conventional pulse-compression scheme was not fea- sible with the technology available at the time of ALCOR’s inception. Consequently, it was necessary to greatly reduce signal bandwidth while preserving range resolution. This is accomplished in a time- bandwidth exchange technique (originated at the Air- borne Instrument Laboratory, in Mineola, New York) called stretch processing [4], which retains range reso- lution but restricts range coverage to a narrow thirty- meter window. In order to acquire and track targets and designate desired targets to the thirty-meter wideband window, ALCOR has a narrowband wave- form with a duration of 10.2 μsec and bandwidth of 6 MHz. This narrowband waveform has a much larger 2.5-km range data window.
Wideband Radar for Ballistic Missile Defense and Range-Doppler Imaging of Satellites 270 LINCOLN LABORATORY JOURNALVOLUME 12
Отправлено: 05.11.10 03:19. Заголовок: The Haystack system ..
The Haystack system has a number of features that rendered this option extremely attractive. It has a large diameter (120 ft) antenna needed to achieve deep-space ranges. The antenna was designed with Cassegrainian optics and could accommodate plug-in radio-frequency (RF) boxes at the vertex of the pa- raboloidal dish. These boxes supported various com- munications, radio astronomy, and radar functions. The interchangeable boxes are 8 × 8 × 12 ft, which is large enough for the high-power (400 kW peak and 200 kW average) new transmitter and associated mi- crowave plumbing, feedhorns, and low-noise receiv- ers needed for the long-range imaging radar.1 The Haystack antenna surface tolerance allows efficient operation up to 50 GHz, thus readily supporting op- erating at X-band (10 GHz) with a bandwidth of 1024 MHz, and a resulting range resolution of 0.25 m. A system for interchanging ground-based elec- tronics and power sources supporting the various RF boxes was already in place. Using an established facil- ity with existing antenna and prime power sources greatly reduced the cost of the new system, known as the Long Range Imaging Radar, or LRIR [6]. The LRIR, which was completed in 1978, is ca- pable of detecting, tracking, and imaging satellites out to synchronous-orbit altitudes, approximately 40,000 km. The range resolution of 0.25 m is matched by a cross-range resolution of 0.25 m for tar- gets that rotate at least 3.44° during the Doppler-pro- cessing interval. The wideband waveform is 256 μsec long and the bandwidth of 1024 MHz is generated by linear frequency modulation. The pulse-repetition frequency is 1200 pulses per second. The LRIR em- ploys a time-bandwidth exchange process similar to
################################### that of ALCOR to reduce signal bandwidth from ############################## 1024 MHz to a maximum of 4 MHz, corresponding #################################### to a range window of 120 m, while preserving the ################################# range resolution of 0.25 m ####################
kopija iz wische ....
This is accomplished in a time- bandwidth exchange technique (originated at the Air- borne Instrument Laboratory, in Mineola, New York) called stretch processing [4], ################### which retains range reso- lution but restricts range coverage to a narrow thirty- meter window.
To place a target in the wideband window, we first acquire the target with a continuous-wave acquisition pulse that is variable in length from 256 μsec (for short-range targets) to 50 msec (for long-range targets). An acquired target is then placed in active tracking by using 10-MHz- bandwidth chirped pulses, again of variable length, from 256 μsec to 50 msec. The wideband window is then designated to the target. Antenna beamwidth is 0.05°. Figure 3(a) shows an artist’s rendition of the 120-foot Haystack antenna in its 150-foot radome; Figure 3(b) shows a photograph of the LRIR feed horn and transmitter/receiver RF box in the Haystack radome
Отправлено: 05.11.10 03:24. Заголовок: mmw radar A second..
mmw radar
A second 35-GHz tube was also added, which doubled the average transmitted power. These modi- fications increased the signal pulse detection range on a one-square-meter target to over two thousand kilo- meters. System bandwidth was also increased to 2 GHz, resulting in a range resolution of about 0.10 m.
More recently, Lincoln Laboratory has developed and exploited several techniques for improving the 278 LINCOLN LABORATORY JOURNAL VOLUME 12, NUMBER 2, 2000 resolution of wideband coherent radar data. The first technique uses modern spectral-analysis methods for improving resolution relative to the restrictions of conventional Fourier processing. These spectral methods extrapolate signals in a radar-frequency di- mension by a process called bandwidth extrapolation. Each wideband pulse return includes the target fre- quency response over the chirped bandwidth. Mod- ern spectral-estimation techniques are then applied to extend this frequency response synthetically outside this band to a factor ranging from two to three times the bandwidth. This expanded pulse return is then re- compressed to provide finer range resolution (for practical signal-to-noise ratios, an improvement of a factor of two to three in resolution is generally real- ized), and when applied to radar imaging, it provides much improved sharpness in the radar image [9]. The second technique uses signal processing mod- els that correspond to rotating-point motion. The models allow extended coherent processing over wide target-rotation angles, resulting in improved Doppler (cross-range) resolution [10]. For sufficiently large resolution angles and for constant-amplitude scatter- ing centers, extended coherent processing also im- proves the range resolution. Extended coherent pro- cessing essentially aligns and stores radar pulses ob- tained over longer time spans as compared to conven- tional imaging. When combined with bandwidth ex- trapolation, extended coherent processing can achieve enhanced resolution in both range and Doppler (cross-range) spaces. For targets where the radar view- ing angle is at a constant aspect angle to the target’s angular-momentum vector, extended coherent pro- cessing provides high-quality three-dimensional radar images. More recently, the Laboratory has explored the possibility of achieving ultrawideband resolution by using data only over sparse subbands of the full ultra- wide bandwidth. We can view this technique as a gen- eralization of bandwidth extrapolation to multiple bands [10]. Ultrawideband’s potential as a discrimi- nation tool is much more robust, as scatterer-feature identification on a specific target is inherently more accurate when observed over a much wider band- width.
Wideband Radar for Ballistic Missile Defense and Range- Doppler Imaging of Satellites William W. Camp, Joseph T. Mayhan, and Robert M. O’Donnell s Lincoln Laboratory led the nation in the development of high-power wideband radar with a unique capability for resolving target scattering centers and producing three-dimensional images of individual targets. The Laboratory fielded the first wideband radar, called ALCOR, in 1970 at Kwajalein Atoll.
35 ghz /2000 mgz mmw radar s 13.6 metra D antennoj 0.042 gradschirinoj lucha na 35 ghz(0.014 grad na 94 ghz) i razrescheniem 100 mm pri polose 2000 mgz
Отправлено: 05.11.10 03:55. Заголовок: As shown in Figure 1..
As shown in Figure 17, the signal is then downconverted to 60 MHz, input to an automatic- gain control (AGC) network, and band limited to 5 MHz. The resulting 60-MHz signal is once again mixed, to yield a 5-MHz sig- nal at an IF of 5 MHz. This final signal can be succinctly described as (4) where fi/ is the 5-m~ fA is the frequency-encoded range IF, term, and -2.5 MHz < f,, c 2.5 MHz. The resulting signal is sam- pled by a IO-bit 20-MHz A/D converter over the 50-its pulse, resulting in 1000 samples which are input to the digital portion of the pulse-compression system.
For the common situation where R=50, this simplifies to
(9) dBm = 20 LOG Eµ - 107
Emju w mirovoltax
esli priemnik imeet chustwitelnost 0.25 microvolt pri signal / k schumam i iskazenijam 12 db ###############################################################
to 0.25 microvolta = -119 dbm ili 149 dbwatt i pri etom naprjazenii signala na wixode poleznij signal na 12 db(po moschnsoti 16 raz ,po napr 4 raza ) wische chem schum
eto dlja polosi 1000 gerz
A SINAD of 12-dB should provide a comfortable margin for copying voice communications. A skilled listener can probably copy voice signals which have a signal to noise ratio of much less than 12-dB. Very skilled listeners can copy voice signals which are at or below the noise level.
Nov. 4, 2010, 12:30 p.m. EDT Innovative 2GSPS Digitizer Reference Design Reduces Time to Market for Communications, Radar and Test Applications
MILPITAS, CA, Nov 04, 2010 (MARKETWIRE via COMTEX) -- Intersil Corporation /quotes/comstock/15*!isil/quotes/nls/isil (ISIL 13.64, +0.38, +2.87%) today introduced the industry's most power-efficient 12-bit, 2 Gigasample/second (GSPS) digitizer reference design, developed to reduce design time for advanced communications, radar and test systems.
Based on Intersil's ISLA112P50 500 Megasample/second (MSPS) converter, the new 2GSPS reference design meets industry requirements for increased sampling speeds, and eliminates artifacts typically caused by interleaved ADCs. Intersil collaborated with SP Devices to develop the new reference design.
The Intersil reference design demonstrates detailed best practices in a known-good system, providing real-time, FPGA-based digital interleave correction of four ISLA112P50 devices. It features significant signal-to-noise and spurious-free dynamic range performance benefits compared with competing 2GSPS ADCs. The signal-to-noise ratio (SNR) is 65.5dB at a 190MHz input frequency, which represents an improvement of 6dB over competing solutions. Since SNR does not degrade significantly with higher input frequencies, this performance advantage is maintained over the entire bandwidth of the digitizer. Spurious free dynamic range (SFDR) is 81.7dBc at a 190MHz input frequency, an improvement of 13dBc. The reference design provides superior SFDR for input frequencies up to 500MHz.
Four 12-Bit 500MSPS ISLA112P50 devices are interleaved to provide 2GSPS. Full power bandwidth is 750MHz, and ADC- and interleave-related power consumption is just 4.1W. For details on the SP Devices evaluation cards, please visit http://www.spdevices.com/index.php/products2/adx4-evm-2000-12.<\/u><\/a>
When Oversampling and Averaging Will Work The effectiveness of oversampling and averaging depends on the characteristics of the dominant noise sources. The key requirement is that the noise can be modeled as white noise. Please see Appendix B for a discussion on the characteristics of noise that will benefit from oversampling techniques. Key points to consider are [2] [3]: • The noise must approximate white noise with uniform power spectral density over the frequency band of interest. • The noise amplitude must be sufficient to cause the input signal to change randomly from sample to sample by amounts comparable to at least the distance between two adjacent codes (i.e.,1 LSB - please see Equation 5 in Appendix A). • The input signal can be represented as a random variable that has equal probability of existing at any value between two adjacent ADC codes. Note: Oversampling and averaging techniques will not compensate for ADC integral non-linearity (INL). Noise that is correlated or cannot be modeled as white noise (such as noise in systems with feedback) will not benefit from oversampling techniques. ############# Additionally,if the quantization noise power is greater than that of natural white noise (e.g.,ther mal noise),then oversampling and averaging will not be effective. ######################## This is often the case in lower resolution ADC’s. The majority of applications using 12- bit ADC’s can benefit from oversampling and averaging.
each additional required bit of resolution can be achieved via oversampling by a factor of four,and each additional bit will add approximately 6 db of SNR (Equation 3) at the cost of reduced throughput and increased CPU bandwidth.
Texas Instruments teorija i praktika dlja 14 bit 190 msps ADC ############################################ By using three ADCs instead of one, the SNR ideally improves by 4.8 dB, as derived below, which boosts the 14-bit ADC (SNR ∼74dB) to a 16-bit ADC level (SNR ∼79dB).
he averaging technique reduces uncorrelated white noise, but has no effect on distortions inherent to the ADC design that might be common to all three ADCs. If, for example, the ADC creates a large third-order distortion product, it will show up in each ADC used and averaging won't reduce it. Therefore, averaging only improves SNR, but not spurious free dynamic ############################################################################# range (SFDR). ###########
ywelichit SFDR mozno s pomoschju dithering - ....dobawleniaj schuma
Zamer resultata ############
Measurements In order to verify the SNR gain, a board was designed containing three ADS5546 ADCs (14-bit, 190 Msps) and an FPGA that was used to perform a 3:1 averaging function. Using two or three standalone ADC evaluation modules (EVM) for this experiment usually doesn't work as well, because noise coupled into the cable assembly is correlated and, therefore, doesn't average out. ################# Furthermore, if the cables are not matched very well, skew between ADCs adds phase mismatch and further degrades the overall SNR.
Отправлено: 08.11.10 13:04. Заголовок: Powtor With stretc..
Powtor
With stretch processing we are limited to a range extent that is usually smaller than a pulse width. ############################################################## Thus, we couldn’t use stretch processing for search because it requires looking for targets over a large range extent, usually many pulse widths long. ################## We could use stretch processing for track because we already know range fairly well but want a more accurate measurement of ################################################################################### it.
We must point out that, in general, wide bandwidth waveforms, and thus the need for stretch processing, is “overkill” for tracking.
Generally speaking, bandwidths of 1s to 10s of MHz are sufficient for tracking ####################################################
Stretch processing does not relieve the bandwidth requirements on the rest of the radar. ##########################################################
Specifically, the transmitter must be capable of generating and amplifying the wide bandwidth signal, the antenna must be capable of radiating the transmit signal and capturing the return signal, and the receiver must be capable of heterodyning and amplifying the wide bandwidth signal. This poses stringent requirements on the transmitter, antenna and receiver but current technology has advanced to be point of being able to cope with the requirements.
stretch processor has the same range resolution as a matched filter. ###########################################
Thus, the stretch processor encounters a SNR loss of relative to the matched filter. This means that we should be careful about using stretch processing for range extents that are a significant part of the transmit pulse width.
Stretch Processing.Stretch processing is a technique frequently used to pro-
cess wide bandwidth linear FM waveforms. The advantage of this technique is that it allows the effective IF signal bandwidth to be substantially reduced, allowing digitiza- tion and subsequent digital signal processing, at more readily achievable sample rates. By applying a suitably matched chirp waveform to the receiver first LO, coincident with the expected time of arrival of the radar return, the resultant IF waveform has a significantly reduced bandwidth for targets over a limited range-window of inter- est. Provided that the limited-range window can be tolerated, a substantially reduced processing bandwidth allows more economical A/D conversion and subsequent digital signal processing. It also allows a greater dynamic range to be achieved with lower- rate A/D converters than would be achievable if digitization of the entire RF signal bandwidth were performed.
If the LO chirp rate is set equal to the received signal chirp rate of a point target, the resultant output is a constant frequency tone at the output of the stretch processor receiver, with frequency∆tB/T, where∆t is the difference in time between the received signal and the LO chirp signal, andB/T is the waveform chirp slope (chirp bandwidth/ pulse width). Target doppler is maintained through the stretch processing, producing an output frequency offset equal to the doppler frequency, though the wide percentage bandwidth often used means that the doppler frequency can change significantly over the duration of the pulse.
Ignoring the effect of target doppler, the required RF signal bandwidth is equal to the transmitted waveform bandwidth. Given the RF signal bandwidthBR, the received pulse widthTR, and the range interval∆T, the required LO reference waveform dura- tion is given by
Отправлено: 08.11.10 20:40. Заголовок: Effect of Characteri..
Effect of Characteristics on Performance.Noncoherent pulse radar perfor-
mance is affected by front-end characteristics in three ways. Noise introduced by the front end increases the radar noise temperature, degrading sensitivity, and limits the maximum range at which targets are detectable. Front-end saturation on strong signals may limit the minimum range of the system or its ability to handle strong interference. Finally, the front-end spurious performance affects the susceptibility to off-frequency interference.
Coherent radar performance is even more affected by spurious mixer characteris- tics. Range and velocity accuracy is degraded in pulse doppler radars; stationary target cancellation is impaired in MTI (moving-target indication) radars; and range sidelobes are raised in high-resolution pulse compression systems.
Modern radar systems are mostly designed to maxi- mize the linear operating region, with limiters used only to handle excessively large signals that inevitably exist under worst case conditions.
Applications.The I/Q demodulator, also referred to as a quadrature channel
receiver, quadrature detector, synchronous detector, or coherent detector, performs fre- quency conversion of signals at the IF frequency to a complex representation,I+ jQ centered at zero frequency. The baseband in-phase (I) and quadrature-phase (Q) signals are digitized using a pair of A/D converters providing a representation of the IF signal, including phase and amplitude without loss of information. The resulting digital data can then be processed using a wide variety of digital signal-processing algorithms, depend- ing on the type of radar and mode of operation. Processing such as pulse compression, doppler processing, and monopulse comparison, all require amplitude and phase infor- mation. The predominance of digital signal processing in modern radar systems has led to almost universal need for Nyquist rate sampled data. In many modern radar systems, digitalI andQ data is now generated using IF sampling followed by digital signal pro- cessing used to perform the baseband conversion as described in Sections 6.10 and 6.11. I/Q demodulators are still used, though their use is increasingly limited to wider band- width systems where A/D converters are not yet available with the required combination of bandwidth and dynamic range to perform IF sampling.
RADAR RECEIVERS 6.35 DC Offset.Small signals and receiver noise can be distorted by an offset in the mean value of the A/D converter output unless the doppler filter suppresses this component.
False-alarm control in receivers without doppler filters is sometimes degraded by errors of a small fraction of the least significant bit (LSB), so correction is preferably applied at the analog input to the A/D. DC offsets can be measured using digital pro- cessing of the A/D converter outputs and a correction applied using D/A converters, as shown in Figure 6.13. DC offset correction can also be performed effectively in the digital domain, provided that the DC offset at the input of the A/D converter is not so large that it results in a significant loss of available dynamic range.
Many of the I/Q demodulator errors described above are either reduced dramati- cally or eliminated using IF sampling. This, along with the reduction of hardware required, are the reasons that IF sampling (described in Sections 6.10 and 6.11) is becoming the dominant approach. 6.10 ANALOG-TO-DIGITAL CONVERTERS
The high-speed A/D converter is a key component in receivers of modern radar sys- tems. The extensive use of digital signal processing of radar data has resulted in a demand for converters with both state-of-the-art sampling rates and dynamic range.
Analog to digital converters transform continuous time analog signals into discrete time digital signals. The process includes both sampling in the time domain, convert- ing from continuous time to discrete time signals and quantization, converting from continuous analog voltages to discrete fixed-length digital words. Both the sampling and quantization process produce errors that must be minimized in order to limit the radar performance degradation. In addition, a variety of other errors such as additive noise, sampling jitter, and deviation from the ideal quantization, result in non-ideal A/D conversion. Applications.The conventional approach of using a pair of converters to digi-
tize theI andQ outputs of an I/Q demodulator is, in many cases, being replaced by digital receiver architectures where a single A/D converter is followed by digital signal processing to generateI andQ data. Digital receiver techniques are described in Section 6.11.
Although the dividing line is arbitrary and advancing with the state-of-the-art, radar receivers are often classified as either wideband or high dynamic range. Different radar functions put a greater emphasis on one or the other of these parameters. For example, imaging radars put a premium on wide bandwidth, whereas pulse doppler radars require high dynamic range. Because radars are often required to operate in a variety of modes with differing bandwidth and dynamic range requirements, it is not uncommon to use different types of A/D converter, sampling at different rates for these different modes. Data Formats.The most frequently used digital formats for A/D converters are 2’s complement and offset binary.10 The 2’s complement is the most popular method of digital representation of signed integers and is calculated by complementing every bit of a given number and adding one.
The Gray code10 is also used in certain high-speed A/D converters in order to reduce the impact of digital output transitions on the performance of the A/D con- verter. The Gray code allows all adjacent transitions to be accomplished by the change of a single digit only. Delta-Sigma Converters.Delta-sigma converters differ from conventional
Nyquist rate converters by combining oversampling with noise-shaping techniques to achieve improved SNR in the bandwidth of interest. Noise shaping may be either low- pass or bandpass depending on the application. Delta-sigma architectures provide poten- tial improvements in spurious-free dynamic range (SFDR) and SNR over conventional Nyquist converters where tight tolerances are required to achieve very low spurious performance. Digital filtering and decimation is required to produce data rates that can be handled by conventional processors. This function is either performed as an integral part of the A/D converter function or can be integrated into the digital downconversion function used to generate digitalI andQ data, as described in Section 6.11. Performance Characteristics.The primary performance characteristics of A/D
converters are the sample rate or usable bandwidth and resolution, the range over which the signals can be accurately digitized. The resolution is limited by both noise and distortion and can be described by a variety of parameters.
Отправлено: 08.11.10 21:03. Заголовок: 6.11 DIGITAL RECEIVE..
6.11 DIGITAL RECEIVERS
The availability of high-speed analog-to-digital converters capable of direct sam- pling of radar receiver IF signals has resulted in the almost universal adoption of digital receiver architectures over conventional analog I/Q demodulation. In a digital receiver, a single A/D converter is used to digitize the received signal, and digital signal processing is used to perform the downconversion toI andQ baseband sig- nals. Continuing advances in sampling speeds are leading to sampling at increasing frequencies, sometimes eliminating the need for a second downconversion, with the possibility approaching of sampling directly at the radar RF frequency. The benefits of IF sampling over conventional analog I/Q demodulation are
●Virtual elimination ofI andQ imbalance ●Virtual elimination of DC offset errors ●Reduced channel-to-channel variation ●Improved linearity ●Flexibility of bandwidth and sample rate ●Tight filter tolerance, phase linearity, and improved anti-alias filtering ●Reduced component cost, size, weight, and power dissipation
The use of a high IF frequency is desirable as it eases the downconversion and filtering process; however, the use of higher frequencies places greater demands on the performance of the A/D converter. Direct RF sampling is considered the ulti- mate goal of digital receivers, with all the tuning and filtering performed through digital signal processing. The advantage being the almost complete elimination of analog hardware. However, not only does the A/D converter have to sample the RF directly, but unless it is preceded by tunable RF preselector filters, the A/D converter input must have the dynamic range to handle all of the signals pres- ent in the radar band simultaneously. Generally, the interference power entering the A/D converter is proportional to the bandwidth of components in front of the A/D converter. The required A/D converter SNR to avoid saturation on the interfer- ing signals is given by
The crest factor is the peak level that can be handled within the full-scale range of the A/D converter relative to the rms interference level. It is set to achieve a sufficiently high probability that full-scale will not be exceeded. For example, with gaussian noise, a crest factor of 4 sets the peak level at the 4s level (12 dB above the rms level) with a probability of 0.999937 that the full-scale is not exceeded on each A/D converter sample. Setting the system noise level power spectral density into the A/D converterR(dB) above the A/D converter noise give
The generation of basebandI andQ signals from the IF sampled A/D converter data is performed using digital signal processing and can be implemented through a variety of approaches.7 Two approaches are described next. Digital Downconversion.The digital downconversion approach is shown in
Figure 6.17. The signal is sampled by the A/D converter, frequency shifted to base- band, low-pass filtered, and decimated to produce I/Q digital data. The signal spectrum at each stage of the process is shown in Figure 6.18. In continuous-time (Fig. 6.18a), frequency is in hertz and is represented byF. In discrete-time (Fig. 6.18b–e), fre- quency is in radians per sample and is represented byw. The spectrum of the ana- log input signalx(t) is shown in Figure 6.18a, with the signal spectrum centered at F0hertz. The signal is sampled by the A/D converter at frequency Fs, producing the time sequence x n ( )and frequency spectrum X( ) ωcentered at frequencyw0 with the image centered at−w0. The A/D converter output signal is then frequency shifted by complex multiplication with the reference signalej n −w0, corresponding to a reference signal rotating atw0 radians per sample, centering the signal spectrumX( ) wabout
zero. The unwanted image is re-centered at−2w0 ifw0> p /2 or−2w0+ 2p ifw0≤ p /2. The unwanted image is then rejected using the FIR filter with impulse responseh(n) producing outputˆ( ) x n with spectrumˆ( ) Xw. Finally, the sample rate is reduced by
RADAR RECEIVERS 6.45 provide the desired stopband rejection response. Thekth order CIC filter for decima- tion factorD has transfer function: Hz z zz K m mD K DK ( )= =−− − =− −− ∑01 1 11 (6.49)
A polyphase filter is a filter bank that splits an input signal intoD sub-band filters operating at a sample rate reduced by a factorD, providing a computationally efficient approach to performing the FIR filtering followed by decimation in a digital receiver. Rather than computing all the filter output samples and only using everyDth sample, the polyphase approach calculates only those that are actually used. Figure 6.22 and Eq. 6.50 define how the filter with impulse responseh(n), followed with decimation by factorD, is implemented in a polyphase structure. The input signalx(n) is divided intoD parallel paths by the “commutator,” which outputs samples in turn, rotating in a counterclockwise direction, to each of the FIR filters operating at the reduced sample rate. The outputs of the FIR filters are summed to produce the output signaly(m). This architecture is beneficial as it provides an approach that can be easily parallelized at rateFX /D. pk(n) = h(k+ nD) k= 0, 1, …,D- 1 (6.50) n=0, 1, …, K-1 Multi-Channel Receiver Considerations.Modern radar systems rarely con-
tain only one receiver channel. Monopulse processing, for example, requires two or more channels to process sum and delta signals. Additionally, the channels must be coherent, synchronized in time, and well matched in phase and amplitude. Digital beamforming systems require a large number of channels with similar coherence and synchronization requirements and tight phase and amplitude track- ing. The coherence requirement dictates the relative phase stability of LO and A/D converter clock signals used for each receive channel. The time synchroniza- tion requirement means that A/D converter clock signals for each channel must be aligned in time and decimation must be performed in phase for each channel. Phase and amplitude imbalance between channels is a result of variation in the
Отправлено: 17.11.10 00:14. Заголовок: Capturing a signal b..
Capturing a signal bandwidth of 30MHz requires an ADC with a sample rate of at least 60Msps. However if the signal was sampled at a higher rate of 120Msps the broadband noise fl oor is reduced by 3dB as given by the following equation
SNR Improvement (dB) = 10 x log (Sampling Rate/2x Signal Bandwidth)
polosa radara (tipa F-22) w zawisimosti ot zadachi ********************************************
Waveform Variations by Mode.Although the specific waveform is hard to pre-
dict, typical waveform variations can be tabulated based on observed behavior of a number of existing A-S radar systems. Table 5.1 shows the range of parameters that can be observed as a function of radar mode. The parameter ranges listed are PRF, pulse width, duty cycle, pulse compression ratio, independent frequency looks, pulses per coherent processing interval (CPI), transmitted bandwidth, and total pulses in a Time-On-Target (TOT).
Obviously, most radars do not contain all of this variation, but modes exist in many fighter aircraft, which represent a good fraction of the parameter range. Most fighter radars are frequency agile since they will be operated in close proximity to similar or identical systems. The frequency usually changes in a carefully controlled, completely coherent manner during a CPI.8 This can be a weakness for certain kinds of jamming since the phase and frequency of the next pulse is predictable. Sometimes to counter- act this weakness, the frequency sequence is pseudorandom from a predetermined set with known autocorrelation properties, for example, Frank, Costas, Viterbi, P codes.16 A major difficulty with complex wideband frequency coding is that the phase shift- ers in a phase scanned array must be changed on an intra- or inter-pulse basis greatly complicating beam steering control and absolute T/R channel phase delay. Another challenge is minimizing power supply phase pulling when PRFs and pulsewidths vary over more than 100:1 range. MFAR systems not only have a wide variation in PRF and pulsewidth but also usually exhibit large instant and total bandwidth. Coupled with the large bandwidth is the requirement for long coherent integration times. This requirement naturally leads to extreme stability master oscillators and ultra low-noise synthesizers.44
Texas Instruments op amp delivers industry's lowest distortion for driving high-speed 16-bit ADCsMonday September 13, 2010 - 08:00 AM EDT PRNewsWire News ReleasesReleased By Texas Instruments Incorporated New op amp maximizes performance across the signal chain for wireless broadband communications, high-speed data acquisition Share:
Rating:
Text Size: DALLAS, Sept. 13 /PRNewswire/ -- Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced a high-linearity, low-distortion, fully-differential operational amplifier (op amp) that delivers 16-bit full-scale precision up to 200 MHz IF to ############################################################################# maximize signal chain performance for wireless base stations, high-speed data acquisition, test and measurement, medical imaging and defense applications. ##############################
The THS770006 op amp has an output third-order intercept (OIP3) of 48 dBm and the lowest distortion in its class, with a third-order intermodulation distortion (IMD3) of -107 dBc at 100 MHz, at least 14 dB better than competitive amplifiers. For more information and to order samples of the THS770006 op amp, visit www.ti.com/ths770006-pr.
"The advancements we've made in the performance of the THS770006 op amp will enable greater levels of receiver dynamic range in wireless systems – a requirement for base station manufacturers to meet the adjacent channel rejection and blocker requirements of next-generation networks," said Steve Anderson, senior vice president of TI's High-Performance Analog business unit. "Our customers can have confidence knowing the THS770006 op amp will help them realize the full potential of their high-speed signal chain."
Key features and benefits
Best-in-class distortion and high linearity help designers meet the stringent sensitivity and bit-error rate (BER) requirements of emerging wireless standards, such as LTE and multi-carrier GSM. Seamlessly drives TI high-speed analog-to-digital converters (ADCs) – including the new 16-bit, 130-MSPS ADS5493 – with full-scale, 3-V peak-to-peak dynamic range for optimal design flexibility and signal-to-noise ratio (SNR) performance. Provides fast overdrive recovery of 7.5 ns (maximum) to help minimize the impact of lost or erroneous data from jammers and blockers, resulting in improved wireless receiver signal integrity. Speeds time-to-market when combined with TI's complete high-speed signal chain portfolio – including high-performance multicore C6000™ DSPs, high-speed ADCs like the ADS5493 and ADS4149, and clocking solutions such as the CDCE72010 – for wireless base stations, high speed data acquisition, test and measurement, medical imaging and defense applications.
Availability and pricing
The THS770006 op amp is available now in a 4-mm x 4-mm QFN-24 package with a thermal pad. Pricing starts at $4.10 in 1,000-unit quantities. The THS770006EVM evaluation module is also available now, priced at $99.
Samples of the ADS5493 ADC are available today. The ADS5493EVM evaluation module is also available now, priced at $299. Production quantities of the ADS5493 ADC will be available in first quarter 2011 in a 7-mm x 7-mm QFN-48 package with a thermal pad. Pricing will start at $65 in 1,000-unit quantities.
Learn more about TI's signal chain portfolio by visiting the links below:
Order THS770006 op amp evaluation modules and samples: www.ti.com/ths770006-pr Download TI's new signal chain selection guide: www.ti.com/signalchain-pr Download TI's updated communications infrastructure solutions guide: www.ti.com/ciguide Learn about "Input impedance matching with fully differential amplifiers" by viewing Jim Karki's short video at www.ti.com/inputimpedance-pr
About Texas Instruments
Texas Instruments (NYSE: TXN) helps customers solve problems and develop new electronics that make the world smarter, healthier, safer, greener and more fun. A global semiconductor company, TI innovates through manufacturing, design and sales operations in more than 30 countries. For more information, go to www.ti.com.
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Отправлено: 22.11.10 23:57. Заголовок: Skorostnie Oy razrab..
Skorostnie Oy razrabatiwaet FGUP Pulsar (Prokopenko) . O Rossijskix AZP nichego ne slischno ...
staraya stat'ya
БЫСТРОДЕЙСТВУЮЩИЕ АНАЛОГОВЫЕ МИКРОСХЕМЫ НА БАЗЕ ВЫСОКОЧАСТОТНОЙ КОМПЛЕМЕНТАРНОЙ БИПОЛЯРНОЙ ТЕХНОЛОГИИ
Р.Н. Виноградов, С.В. Корнеев, Д.Л. Ксенофонтов
Цифровая электроника захватывает все большие сферы обработки аналогового сигнала, что, естественно, приводит к снижению относительной доли аналоговых микросхем в полупроводниковой элементной базе. Тем не менее, прогресс технологии полупроводниковых микросхем приводит к расширению номенклатуры, повышению частотного диапазона и расширению областей применения аналоговых микросхем в тех областях, где широко использовались дискретные полупроводниковые компоненты.
Преобразование аналогового сигнала в цифровой код определяется точностными и частотными ограничениями аналого-цифровых преобразователей (АЦП). Если после АЦП обработка сигнала происходит в цифровой форме и построена полностью на монолитных микросхемах, то в предварительной аналоговой обработке до сих пор широко используют дискретные приборы т.к. аналоговая микроэлектроника часто не удовлетворяет предъявляемым требованиям.
В настоящее время отсутствие отечественных высокочастотных микросхем для аналоговой обработки сигнала, начинает восполняться новыми разработками в области создания быстродействующих аналоговых микросхем серии К1432, проводимыми в ГУП ”НПП ”Пульсар”
БиКМОП SiGe • Проектная норма – 250 нм (2011 год) • Проектная норма – 180 нм (2012 год) • СВЧ и УВЧ до 10ГГц (АФАР, конвертеры и синтезаторы для радиолокационных систем и спутниковой связи) ##########################################################################
Отправлено: 23.11.10 00:40. Заголовок: ОАО «НИИМЭ и Микрон»..
ОАО «НИИМЭ и Микрон»
1996 – 2000
Разработаны и освоены быстродействующие ЦАП и АЦП схемы серии 572. Освоено более 200 типов интегральных схем, ранее выпускавшихся на других предприятиях страны.
Отправлено: 23.11.10 13:03. Заголовок: проектирование анало..
проектирование аналоговых и цифровых СФ-блоков, в том числе: встраиваемых АЦП, ЦАП, ФАПЧ, микропроцессорные ядра, аппаратные вычислители и различные интерфейсы;
Дизайн-центр имеет соответствующий сертификат от 22 НИИ МО РФ.
Новости ФГУП "НИИЭТ" ФГУП "НИИЭТ" (г. Воронеж) в рамках ОКР "Номенклатура" завершает разработку серии мощных СВЧ LDMOS транзисторов 2П998А (РВЫХ=35 Вт), 2П998БС (РВЫХ =150 Вт) для применения в диапазоне рабочих частот до 500 МГц с напряжением питания 28 В. Транзисторы предназначены для комплектования усилительных модулей аппаратуры стационарных и бортовых средств связи специального и двойного назначения. Модули с использованием LDMOS транзисторов позволят увеличить энергетические параметры аппаратуры и её функциональные возможности. Подробнее смотрите на сайте www.niiet.ru . Предприятие принимает предварительные заявки заинтересованных потребителей на поставку транзисторов с видом приёмки "5" начиная с августа 2010 года. ФГУП «НИИЭТ» (г. Воронеж) завершил разработку серии мощных СВЧ низковольтных LDMOS транзисторов 2П986А, 2П986Б, 2П986В, 2П986Г для применения в диапазоне рабочих частот до 1 ГГц и транзисторов 2П986Д, 2П986ЕС для применения в диапазоне частот до 650 МГц. Подробнее смотрите на сайте www.niiet.ru
В рамках ФЦП "Развитие электронной компонентной базы и радиоэлектроники" на 2008-2015 годы ФГУП "НИИЭТ" закончил разработку первой отечественной СБИС 16-разрядного микроконвертера. Микросхема построена на базе усовершенствованного ядра архитектуры MCS-96. Высокая скорость выполнения арифметических и логических операций достигается благодаря наличию встроенного аппаратного умножителя (умножение 16×16 – 1 машинный цикл), делителя (деление 32/16 – 2 машинных цикла), сдвигателя (любой сдвиг – 1 машинный цикл). В состав микроконвертера входят восемь параллельно работающих 16‑разрядных АЦП, #####################################################
Kakix ?
14‑разрядный ЦАП со временем установления выходного тока не более 11 нс, ОЗУ общего назначения объёмом 1000 байт, расширенное ОЗУ (XRAM) объёмом 2048 байт, FLASH память программ – 32 Кбайта, периферийные устройства – UART, блок высокоскоростного ввода-вывода (HSI/HSO), аппаратный ШИМ, сервер периферийных транзакций (PTS) и др. В микросхему встроен модуль отладки OCDS. По системе команд микроконвертер совместим с серийно выпускаемыми предприятием микроконтроллерами серии 1874. Изготовление образцов микроконвертера планируется в I квартале 2010 года.
Отправлено: 23.11.10 21:19. Заголовок: Помимо того, что наш..
Помимо того, что наша продукция сертифицирована по системе "Оборонсертифика", научно-исследовательский центр "РИФ" имеет Лицензию ФСБ на осуществление различных видов деятельности. Поэтому разработки ЗАО "НТЦ "РИФ" проходят несколько уровней контроля качества (от обычных лицензий до военной приемки).
Важным направлением нашей работы является производство измерительных устройств и устройств цифро-аналоговых преобразований (АЦП и ЦАП), которые продолжают находить широкое применение во многих областях научно-технических разработок.
Проекты ЗАО "НТЦ "Риф"
1 Система управления средствами ПВО 2 Ремонтный завод МР4 3 Комплекс сопряжения корабельных систем 4 Модель РЛС с АФАР
Отправлено: 24.11.10 23:01. Заголовок: LOCKHEED MARTIN USES..
LOCKHEED MARTIN USES DIGITAL BEAMFORMING TECHNOLOGY TO REDEFINE RADAR STATE-OF-THE-ART
MOORESTOWN, NJ, January 15th, 2008 -- Lockheed Martin [NYSE: LMT] successfully demonstrated digital beamforming (DBF) capability to locate and track live targets with its Scalable Solid-State S-band Radar (S4R) engineering development model.
DBF is the most advanced approach to phased-array antenna pattern control. It provides significant performance advantages over conventional analog beamforming techniques, including improved operations in severe environmental clutter and, through the use of multiple simultaneous beams, increased search and track timeline efficiency.
“Our S4R demonstration successes are quickly moving next generation radar technology – such as digital beamforming – from the laboratory to the fleet,” said Carl Bannar, vice president and general manager of Lockheed Martin’s Radar Systems line of business. “S4R will bring a huge radar technology leap to next generation multi-mission radars, ranging from littoral operations to ballistic missile defense.”
The S4R engineering development model is an active, electronically-steered digital array radar designed to be scalable to support multiple missions, including air surveillance, cruise missile defense, ballistic missile defense, counter target acquisition and littoral operations. The proven digital array radar design is derived from the S-band antenna developed for the U.S. Navy’s next-generation destroyer. The DBF signal processor was derived from the Aegis Ballistic Missile Defense signal processor.
The S4R engineering development model was developed using Silicon Carbide (SiC)- based high-power Transmit/Receive modules. SiC provides greater power than other commonly used materials due to its increased heat tolerance. With more power, the radar has longer range and provides more precise target discrimination.
This S4R milestone continues Lockheed Martin’s legacy of advanced naval radar development. The SPY-1 radar, the pre-eminent radar at sea today, is on 83 Aegis-equipped warships around the world, and is the main sensor for the Aegis Ballistic Missile Defense Weapon System.
Headquartered in Bethesda, MD , Lockheed Martin employs about 140,000 people worldwide and is principally engaged in the research, design, development, manufacture, integration and sustainment of advanced technology systems, products and services.
Media contact:Ken Ross, 856-722-6941; cell 856-912-5802; kenneth.b.ross@lmco.com
Отправлено: 25.11.10 15:16. Заголовок: 8B. 3 A GENERIC RADA..
8B. 3 A GENERIC RADAR ... within the FPGA, a wide range of radar intermediate ... down converter as well as any oversampling that takes place within the radar ...
Model 71621 3 kanala s ADS5485 200 msps /16 bit TI
IF 120-160 mgz
To conserve resources, we will try an undersampling solution for digitizing the input signals. If we sample at 200 MHz, the signals of interest will fold as shown in Figure 7: the 120 MHz lower band edge translates to 80 MHz; the 140 MHz center frequency translates to 60 MHz; and the upper band edge translates to 40 MHz.
Отправлено: 29.11.10 22:33. Заголовок: A great deal of the ..
A great deal of the technological groundwork for this process was established during 1971. By 1972, fabrication of the first reflective-array compressor (RAC) was initiated; this device is illustrated in Figure 2. The first RAC device was a linear-FM filter with a 50-MHz bandwidth (on a 200-MHz carrier) matched to a 30-μsec-long waveform [16–18]. This arrangement yielded a time-bandwidth product of 1500, more than an order of magnitude greater than that achieved by interdigital-electrode SAW devices [19]. The response was remarkably precise; the phase deviation from an ideal linear-FM response was only about 3° root mean square (rms). Pairs of matched RACs were used in pulse-compression tests in which the first device functioned as a pulse expander and the second as a pulse compressor. The compressed pulsewidths and sidelobe levels were near ideal. Armed with these encouraging results, researchers took the next step by developing RAC devices for specific Lincoln Laboratory radars.
Отправлено: 29.11.10 22:37. Заголовок: The ARPA-Lincoln C-b..
The ARPA-Lincoln C-band Observables Radar, or ALCOR [20], on Roi-Namur, Kwajalein Atoll, Marshall Islands, had a wideband (512 MHz) 10-μseclong linear-FM transmitted-pulse waveform (see the article entitled “Wideband Radar for Ballistic Missile Defense and Range-Doppler Imaging of Satellites,” by William W. Camp et al., in this issue)
The return signal is mixed with a linear-FM chirp and the low-frequency sideband is Fourier transformed to yield range information. For a variety of reasons, the output bandwidth and consequently the range window were limited. For example, the ALCOR STRETCH processor yielded only a thirty-meter data window. *********************************** Therefore, examination of a number of reentry objects, or the long ionized trails or wakes behind some objects, required a sequence of transmissions.
16-битные АЦП-приемники на основе технологии SiP — без лицензии на импорт Действующие экспортные ограничения в области высоких технологий, в том числе на быстродействующие АЦП, серьезно ограничивают российских производителей коммуникационного, измерительного и другого оборудования, в котором могут использоваться подобные АЦП. И хотя лицензию на поставки таких компонентов получить можно, ограничения все равно препятствуют широкому внедрению скоростных АЦП и не дают нашим разработчикам набрать опыт использования устройств такого класса, снижая конкурентоспособность отечественных разработок
Input bandwitch - bolee 1000 mgz SNR -71.5 DB THD -85 db (Vin menee 240 mgz) SFDR -bolee 100 dbfs bez 2 i 3 harmoniki apperturnaja pogr - menee 60 femtosek max vx.signal 4 v(peak to peak)
Collaboration of Intersil and SP Devices Demonstrates 4-way Interleaving of Intersil 500MSPS ISLA112P50s Sample Rate: 2.0 GSPS Resolution: 12 Bits Interleave Correction Details SP Devices’s ADX4 provides real-time, digital, FPGA based digital interleave correction of four ISLA112P50s Performance SNR = 65.5 dBfs @ Fin = 190MHz, a 6dB improvement over current best standalone 2GSPS ADCs SFDR = 82 dBc @ Fin = 190MHz, a 13dB SFDR improvement over current best standalone 2GSPS ADCS http://www.intersil.com/converters/ADC_ref_design.asp<\/u><\/a>
naschel -Rossijskij AZP ,bolee menee prilichnij 2 kanala po 14 bit
20 msps na 140 mgz ,SFDR -90 db
Области применения: Микросхема 9008ВГ1Я предназначена для построения многоканальных систем ввода аналоговых сигналов/изображений. Практическое применение возможно в таких областях, как: § системы ввода изображения, в том числе системы тепловидения; § радиосвязь; § радиолокационные системы; § гидроакустические системы; § измерительная техника; § системы сбора данных; § системы управления; § системы промышленного контроля; § и в других устройствах, позволяющих принимать и обрабатывать отсчеты АЦП в реальном времени. 9008ВГ1Я может быть использов
Отправлено: 06.12.10 14:56. Заголовок: sudja po anonsu 15 m..
sudja po anonsu 15 marta 2010 -eto iz novix
Отечественные 14-разрядные АЦП с частотой оцифровки 20 МГц
В ГУП НПЦ «ЭЛВИС» разработаны микросхемы двухканального аналого-цифрового контроллера ввода сигналов 9008ВГ1Я (макетные образцы имеют маркировку 2008ВГ1Я). Микросхемы выполнены в виде многокристального модуля и содержат два кристалла 14-разрядных АЦП конвейерного типа с частотой оцифровки до 20 МГц и цифровой контроллер. Кристаллы изготовлены по 0,25-мкм технологии и размещены в корпусе BGA-192 размером 17x17 мм. Диапазон рабочих температур микросхем — от –60 до +85 oC.
9008ВГ1Я предназначены для построения многоканальных систем ввода аналоговых сигналов и могут быть использованы в качестве замены AD9225, AD9240, ADS850 (Analog Devices) и LTC2246, LTC2226 (Linear Technology).
Sandia receives DoD ‘trusted foundry’ accreditation ALBUQUERQUE, N.M. —Sandia National Laboratories’ silicon fabrication facility in Albuquerque, N.M., has been accredited by the Department of Defense (DoD) to provide “trusted foundry” services for both unclassified and classified integrated circuits. The foundry accreditation represents an increase in scope to Sandia’s already-existing accreditation for design services.
The accreditation program is part of DoD’s strategy to ensure that electronic components used in U.S. military and national security applications are trustworthy. Certification is necessary because the increasing offshore migration of all sectors of the microelectronics industry comes at a time of increasing demand for high-performance, application-specific integrated circuits (ASICs) from U.S. military and national security agencies.
Sandia’s Category 1A status, which requires the most stringent protection measures, was awarded through the Trusted IC Supplier Accreditation Program of the DoD’s Defense MicroElectronics Activity (DMEA).
The trusted foundry accreditation is for Sandia’s strategically radiation-hardened, 3.3-volt, 0.35-micrometer, SOI (Silicon-on-Insulator) CMOS ----------------------------------------------------------------------------------------------------------------------------------------------------------------- (a widely used type of semiconductor) process which produces custom low-volume, high reliability ASICs. Sandia’s silicon fab is optimized for radiation-hardened, analog and mixed-signal microelectronics, custom digital ASICs and discrete devices. Sandia uses 0.35-micrometer geometry to optimize performance for analog circuits resulting in better device matching, higher supply voltages and broader signal dynamic range than smaller geometry devices. Properly designed and fabricated, larger devices are more likely to continue to perform in extended operating environments of temperature fluctuations, shock and radiation.
In support of its primary mission as steward of the U.S. nuclear stockpile, Sandia has developed and delivered microelectronic products for nearly three decades. This expertise has also been applied to other national security needs. These include ensuring the nonproliferation of nuclear weapons and materials, reducing the threat from chemical and biological weapons, and providing advanced custom designs for other agencies involved in national defense. Sandia’s ASIC development team provides custom microelectronic products and engineering services that fulfill the needs of a diverse set of customers.
Sandia focuses on high-reliability custom solutions for high-consequence applications. An efficient and disciplined ISO 9001 certified process enhances chances for silicon solutions successful on a first pass-through. Sandia offers a total supply-chain solution for radiation-hardened integrated circuits and microsystems by combining trusted ASIC design and fabrication with other in-house capabilities in packaging, test, failure analysis and reliability.
For further information or questions, visit www.sandia.gov/mstc/ or email Trusted_ASIC@sandia.gov.
-------------------------------------------------------------------------------- Sandia National Laboratories is a multiprogram laboratory operated by Sandia Corporation, a wholly owned subsidiary of Lockheed Martin, for the U.S. Department of Energy’s National Nuclear Security Administration. With main facilities in Albuquerque, N.M., and Livermore, Calif., Sandia has major R&D responsibilities in national security, energy and environmental technologies, and economic competitiveness.
Sandia media relations contact: Neal Singer, nsinger@sandia.gov (505) 845-7078
http://www.armstrade.org/includes/periodics/news/2011/0305/18007421/detail.shtml Юрий Борисов назначен первым заместителем председателя Военно-промышленной комиссии ЦАМТО, 5 марта. Премьер-министр РФ Владимир Путин распоряжением №353-р от 3 марта 2011 года назначил первым заместителем председателя Военно-промышленной комиссии при правительстве РФ Юрия Борисова, освободив его от должности замминистра промышленности и торговли.
Борисов Юрий Иванович родился 31 декабря 1956 года в г. Вышний Волочек Калининской области.
Выпускник Калининского суворовского военного училища 1974 года.
Окончил Пушкинское высшее командное училище радиоэлектроники ПВО в 1978 году и Московский государственный университет им. М.В.Ломоносова в 1985 году. Доктор технических наук.
1974-1978 гг. - курсант Пушкинского высшего командного училища радиоэлектроники ПВО.
1978-1998 гг. - служба на офицерских должностях в Вооруженных силах СССР, Российской Федерации.
1998-2004 гг. - генеральный директор ЗАО Научно-технического центра «Модуль».
С июля 2004 г. по октябрь 2007 г. - начальник Управления радиоэлектронной промышленности и систем управления Федерального агентства по промышленности.
С 19 октября 2007 г. - заместитель руководителя Федерального агентства по промышленности.
2 июля 2008 года распоряжением правительства Российской Федерации № 960-р был назначен заместителем министра промышленности и торговли РФ.
Награжден Орденом «За службу Родине в Вооруженных Силах СССР» III степени и медалями.
Отправлено: 15.04.11 18:58. Заголовок: 18 апреля 2011 г. Го..
18 апреля 2011 г. Государственная Дума
НАЧАЛО: 11.00 Малый зал.
Комитет по промышленности проводит «парламентские слушания», посвященные наиболее острым и важным вопросам законодательного обеспечения развития электронной промышленности в России.
Председатель Комитета Государственной Думы по промышленности, депутат фракции КПРФ С.В. Собко сформулировал задачу предстоящих парламентских слушаний следующим образом: «Сегодня надо говорить откровенно, отставание России в развитии элементной базы становится критическим. Это не просто экономическая проблема, это проблема национальной безопасности. Наши ракеты летают на микросхемах, купленных на Митинском рынке. Промышленная модернизация невозможна без создания собственной элементной базы. В плане законотворческой работы здесь огромное поле для деятельности».
По итогам парламентских слушаний будут приняты рекомендации, которые содержат комплекс законодательных инициатив и предложений для органов федеральной исполнительной власти.
Applications • Radar Array Processing • Software Defined Radios • Broadband Communications • High-Performance Data Acquisition • Communications Test Equipment
Functional Description The ISLA216P25 is based upon a 16-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 18). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. Digital error correction is also applied, resulting in a total latency of 10 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs.
Copy from answer of patentholder #######################
Hello ...(milstar)
...Your questions are definitely relevant to the work we do at GMR.
Regarding question 1. The increase in dynamic range is very much dependent on the ADC type and indeed the full RF front end. Our techniques increase the dynamic range for ADCs and/or the entire RF front-end including the ADC. For example in systems where the receiver amplifier (typically a low noise amplifier) is a dominant factor in the linearity we can fix those nonlinearities as well. In addition, we correct for other distortions that are not harmonic in nature. For example, many systems use digitization methods that in effect use interleaving of 2, 4 or more ADCs in parallel thus achieving high sampling rates and high linearity. Unfortunately the interleaving itself is a source of errors that limits the overall dynamic range . GMR's iNLEQ techniques overcome those types of errors.
The specific ADCs you reference (assuming they are working on their own and not interleaved with others per the iNLEQ discussion above) will typically have improvements in dynamic range of about a) 12dB, b) 18dB, and c) 18 dB, respectively. Please note further that while these ADCs appear from the outside to be a single component they are, in fact, internally composed of multiple sampler sub-devices and therefore we use our iNLEQ interleaving error mitigation techniques as well.
Regarding question 2. We certainly use our techniques in addition to other forms of error mitigation. We would need to discuss specifics for me to give you a more definitive answer about how best to make this work for any specific system. We typically collaborate with other companies or organizations to achieve the most cost effective solutions for them.
Please let me know if I can be of further assistance.
Best regards, Gil Raz GMR Research & Technology, Inc.
----------------------------------
Gentlemen
Author of this e-mail have some questions about NLEQ processor perspective . Excuse the author ,if questions are not relevant
Relevant answer would appreciated
1. How great can be dynamic rang extension with NLEQ processor and new ADC
a. ADC9467 16 bit/250 msps b. EV10AS150 10 bit/2.5 gsps c. ADC12D1800 - 12-Bit, Single 3.6 GSPS ADC
2. Is possible combination of NLEQ with another method*s
A Wide Dynamic Range Playback System for Radar Signals
X-Band Receiver The MITEQ X-Band receiver is of a dual conversion superheterodyne architecture that translates a 10 GHz signal with a bandwidth of 1 GHz to an IF center frequency of 70 MHz and a bandwidth of 20 MHz for stretch processing of radar returns. The receiver also includes a wideband IF output at 1 GHz for use with advanced high speed ADC (analog to digital converter) processing techniques such as optical processing, time sequenced ADC arrays, or time stretched ADC arrays
Компания "Ангстрем" и китайский производитель подписали соглашение о совместном производстве телекоммуникационного оборудования Компания "Ангстрем" и китайский производитель Huawei подписали соглашение о совместном производстве телекоммуникационного оборудования, в том числе для строительства сетей LTE. ####################################### Производство будет развернуто на мощностях "Ангстрема" в Зеленограде, его запуск запланирован на IV квартал 2011 г. В перспективе российская компания собирается выпустить линейку оборудования под собственным брендом. До тех пор пока в России не будет решен вопрос о выделении частот под сети четвертого поколения, потенциальным рынком сбыта могут стать страны СНГ. #######################################################################
В рамках соглашения, которое компании подписали вчера, "Ангстрем" будет производить телекоммуникационное оборудование под маркой Huawei на собственной производственной базе в подмосковном Зеленограде. Кроме того, компании будут совместно разрабатывать технологические решения. Начать производство планируется в IV квартале 2011 г., его проектная мощность составит до 10 тыс. изделий в год. ###############################################################################################
W mire 2.2 mln bazowix stanzij wsex modifikazij W Rossii 110 000 bazowix stanzij
Esli w nix budut ispolzowatsja rossijskie GaAS/GaN i rossijskie AZP ############################################
to S.Ivenovu yawnij +
В рамках проекта в 2011 г. "Ангстрем" инвестирует в технологическую базу 400 млн руб. Со своей стороны Huawei предоставит разработки и технологии, подготовит специалистов "Ангстрема" и установит систему контроля качества продукции. Производство и продажу полностью возьмет на себя "Ангстрем", Huawei, в свою очередь, получит лицензионные отчисления.
На первом этапе "Ангстрем" будет производить базовые станции LTE, оборудование DWDM (OSN6800 и OSN1800), оборудование доступа (MA5600T и МА5603Т), IP-switch (S2300 и S3300 + S5300), оборудование РРЛ (серия RTN) и операторские маршрутизаторы (серии NE40/NE80/NEx). ##############
Как рассказал на пресс-конференции президент НПО "Ангстрем" Алексей Таболкин, в дальнейшем компания планирует наладить производство собственной продукции. "Сейчас мы работаем над созданием линейки оборудования под собственным брендом, - сказал он. - Первый этап сотрудничества - это локализация производства". К 2013 г. в Зеленограде будут открыты дополнительные производственные мощности. ########################################################################################
Пока же, по словам Алексея Таболкина, компания проводит маркетинговую работу и изучает рынки сбыта. "Мы планируем в процессе усложнения локализации постепенно менять в собираемом оборудовании импортную микроэлектронику на российскую. #################################################################################
И начнем с интеграции в оборудование Huawei однокристального микропроцессора с функцией навигации ГЛОНАСС/GPS, разработанного на "Ангстреме", - говорит он.
Huawei, в свою очередь, заинтересован в расширении партнерства с российскими производителями. По словам первого заместителя главы российского представительства компании Александра Богданова, Huawei ведет переговоры и с другими компаниями и в дальнейшем рассчитывает иметь несколько партнеров. Пока же китайский производитель ожидает, что сотрудничество с "Ангстремом" позволит ему увеличить свое присутствие на российском рынке.
Компании рассчитывают, что в 2013 г. объем продаж оборудования совместного производства составит около 1 млрд руб. в год. ####################################################################################### Для начала потенциальным рынком сбыта станет Россия, а в дальнейшем - страны СНГ, сказал Алексей Таболкин. "Пока объем производства не такой большой, чтобы осваивать другие рынки", - считает он.
Аналогичное партнерство российского производителя и иностранной компании реализуется в Томской области. Как ранее сообщал ComNews, в марте 2011 г. Nokia Siemens Networks, компания "Микран", администрация Томской области и корпорация "Роснано" подписали соглашение о создании производства оборудования для сетей LTE. ##################################### Mikran izgotowitel GaAS dlja AFAR MiG-35 Его запуск в Томске запланирован на IV квартал этого года, серийный выпуск будет налажен к 2012 г. Первоначальный объем выпускаемой продукции составит около 10 тыс. базовых станций в год (см. новость на ComNews от 15 марта 2011 г.). ##########################################################################
Начало продаж ожидается в IV квартале 2011 г., однако проблема с выделением частот под строительство сетей LTE в России пока не решена. На вопрос о целесообразности таких сроков председатель совета директоров "Ангстрема" Леонид Рейман сказал, что главная цель проекта - организовать производство телекоммуникационного оборудования нового типа, а также провести совместные исследования и разработки. "Производство прежде всего нацелено на Россию, но сети LTE уже есть в других странах СНГ", - сказал он.
Между тем операторы "большой тройки" уже развернули тестовые сети LTE в странах СНГ: МТС - в столице Армении Ереване и в столице Узбекистана Ташкенте, а "ВымпелКом" - в двух столицах Казахстана, Алма-Ате и Астане. Правда, проработали сети в Казахстане недолго, и пока оператор ведет переговоры с регулятором о полноценном запуске. Поставщиком оборудования для проекта "ВымпелКома" в Казахстане выступила компания Alcatel-Lucent. "Партнеры сами обратились к нам с предложением совместно развернуть сеть четвертого поколения, и их оперативность оказалась решающим фактором для начала сотрудничества", - сказал репортеру ComNews руководитель департамента по связям с общественностью в СНГ компании "ВымпелКом" Артем Минаев. По его словам, важным фактором при выборе партнера стал опыт в реализации аналогичных проектов. Например, у Alcatel-Lucent совместно с Verizon запущена сеть LTE в 700-м диапазоне в США. В начале 2011 г. сеть в Алма-Ате была отключена по окончании действия лицензии. "Окончательного решения по LTE нет, но мы ведем совместную работу с регулятором на тему развития в республике сетей связи четвертого поколения", - пояснил ситуацию Артем Минаев.
Executive Summary Like they did last year, Ericsson and Huawei share the top spot in the LTE ranking. The LTE infrastructure market is forecast to grow from approximately $2.5 billion USD in 2011 to $13 billion USD by 2016. ###########################################################
As operators increase their levels of infrastructure investment, all the vendors have reported improved financial performance in 2010 and early 2011. The LTE vendor set is therefore unlikely to be reduced further in the short term, despite previous consolidation trends. The WiMAX vendor set continued to shrink in 2011 as WiMAX loses momentum and is increasingly regarded as legacy technology by operators. Further reductions of the WiMAX vendor set are possible. All major RAN vendors have introduced distributed base stations using centralized baseband processing – so-called baseband farms. These types of deployments are increasingly being adopted by operators. Operators may find that having invested in a baseband farm, they are locked-in to that vendor. Competitors may find that once another vendor deploys a baseband farm, access to that area has been effectively blocked. Early LTE deployments are concentrated among a handful of operators, notably Verizon. This has benefitted Ericsson and Alcatel Lucent above all, who are the only vendors that have deployed commercial-scale networks, giving them a head start in maturing their LTE technology. Huawei and NSN are positioned for future growth due to the large number of LTE contracts they have been awarded. Maravedis notes that many of these contracts are for small trial networks, and do not guarantee future deployments. Huawei has succeeded in penetrating the technologically demanding Western Europe market and has rolled out some of the larger LTE networks. We expect them to become the largest network vendor in the near future. The market for LTE small cells has not yet materialized, in part because vendors don’t have products ready to go to market. Maravedis expects LTE small cell deployments to begin in 2012, with increasing volume in 2013 and 2014. 3G Leapfrogging is not yet a phenomenon in the wireless industry. Maravedis has identified that 21 out of 25 top LTE operators, or 84%, will be moving from HSPA to HSPA+ prior to their evolution to LTE. All vendors are pushing into cloud computing and service delivery. They are becoming increasingly sophisticated solution providers deriving a growing portion of their income from services – installation, engineering, and network operations. The more sophisticated LTE Vendors are working to develop capabilities in their mobile network solutions to drive ARPU, particularly in video services.
Отправлено: 16.06.11 23:12. Заголовок: Hittite's High S..
Hittite's High Speed ADCs Target Digital Storage Oscilloscopes June 3, 2011
Hittite Microwave Corporation, the world class supplier of complete MMIC based solutions for communication & military markets, has introduced three new ADCs that are ideal for Digital Storage Oscilloscopes (DSOs). The combination of low power and 1 GSPS sample rate yields the industry's first ADC solution for 1 GSPS USB powered Oscilloscopes.
The HMCAD1520, HMCAD1511 and HMCAD1510 feature integrated functions which are ideal for DSO applications. Integrated crosspoint switches allow switching between quad, dual and single channel modes, while integrated 1 to 8 x clock dividers keep the input clock frequency constant when the number of channels is changed.
The HMCAD1511 features 8-bit resolution at 1 GSPS sample rate. A 13-bit internal resolution allows up to 32 x (30 dB) of digital gain without missing codes, allowing the user to replace analog gain circuitry with digital gain settings. At 1 GSPS and 710 mW, the HMCAD1511 consumes the industry's lowest power, enabling the implementation of USB powered oscilloscopes up to 1 GSPS.
By interleaving 2 or 4 HMCAD1511 ADCs, overall sample rates of 2 or 4 GSPS can be achieved respectively. The low size and power of HMCAD1511 make it an excellent building block for Oscilloscopes up to 4 GSPS.
The HMCAD1520 provides up to 12-bit resolution at up to 640 MSPS, making it ideal for precision DSOs. The HMCAD1511 is available as an operational mode for the HMCAD1520, allowing combined 12-bit and 8-bit implementations. The HMCAD1510 features 8-bit resolution up 500 MSPS. The device consumes the lowest power in the industry at 295 mW, making it an ideal choice for high performance handheld battery powered oscilloscopes.
All three ADCs can be evaluated with the Hittite EasySuite evaluation kits, EKIT01-AD1520, EKIT-AD1511 and EKIT-AD1510.The evaluation kits are based on Xilinx FMC (FPGA Mezzanine Card) SP601 standard motherboards, and feature Hittite evaluation boards with on-board ADCs connected to the Xilinx board through an FMC connector. Hittite's pre-loaded EasyStack firmware performs FPGA processing, while the EasySuite PC software tool performs ADC configuration, data capture and performance analysis.
The HMCAD1520, HMCAD1511 and HMCAD1510 ADCs are housed in 7 x 7 mm plastic leadless surface mount packages.Samples and Evaluation Kits are available from stock and can be ordered via the company's e-commerce site or via direct purchase order. For more information, visit www.hittite.com.
About Hittite Microwave Corporatio Hittite Microwave Corporation is an innovative designer and manufacturer of high performance integrated circuits, or ICs, modules, subsystems and instrumentation for technically demanding digital, RF, microwave and millimeterwave applications covering DC to 110 GHz. The Company's standard and custom products apply analog, digital and mixed-signal semiconductor technologies, which are used in a wide variety of wireless / wired communication and sensor applications for Automotive, Broadband, Cellular Infrastructure, Fiber Optics & Networking, Microwave & Millimeterwave Communications, Military, Test & Measurement, and Space markets. The Company is headquartered in Chelmsford, Massachusetts.
Отправлено: 23.08.11 16:46. Заголовок: Dannie po zifrowoj o..
Dannie po zifrowoj obrabotke signala 1000 mgz za 1998 god
3.1.2 Radar Data Collection X-Band radar data are collected with Haystack in a staring mode. Four channels are processed in the radar: PP sum, OP sum, PP traverse difference, and PP elevation difference. Data from all four channels are coherently converted to a 60-MHz intermediate frequency, filtered to 1-MHz bandpass, further downconverted to 5 ± 0.5 MHz, and then digitized at a rate of 20 MHz using a 10-bit digitizer. In-phase (I) and quadrature (Q) data are created at a 5-MHz sample rate, and then thinned without averaging to a 1-MHz rate. Using about a 40% range overlap, the I and Q samples are fast Fourier transformed (FFT) to the frequency domain. Complex FFT data for each channel are sent to a memory buffer containing data for the previous 12 to 20 pulses. To minimize the archiving of data with no detections, a noncoherent 12-pulse running sum of the PP sum channel data is maintained, and only when a threshold is exceeded are the spectral data for all four channels permanently recorded to tape. The recording threshold is intentionally set lower than allowed in subsequent processing to ensure that no usable data are missed.
Hittite’s 18 GHz Ultra Wideband Track-and-Hold Amplifier Enhances High Speed ADC Performance By Hittite Microwave
Wideband data acquisition systems with multi-GHz bandwidth are needed for a variety of applications such as software defined radio, radar systems, Electronic Warfare (EW) / Electronic Intelligence (ELINT) and test and measurement equipment. Ideally, system designers would like to be able to connect the signal source (for example an antenna) directly to a wideband, high dynamic range Analog-to-Digital Converter (ADC) for digitization. http://www.mpdigest.com/issue/Articles/2011/apr/hittite/Default.asp
Although several high speed ADCs offer enhanced sample rates, few of them offer input bandwidth beyond a few GHz. In addition, maintenance of good sampling linearity at frequencies above the UHF band is technologically challenging and most current ADCs suffer rapidly degrading linearity above 1 or 2 GHz signal frequency. These limitations result from the Track-and-Hold Amplifier (THA) which sample the input signal at a precise time instant and holds the value of the sample constant during the analog-to-digital conversion. This THA (integrated into the ADC) is often not optimized for ultra wideband operation. These limitations can be overcome by using Hittite’s HMC5640BLC4B Ultra Wideband Track-and-Hold Amplifier, which is designed for use in microwave data conversion applications requiring maximum sampling rate, low noise and high linearity over a wide bandwidth.
The HMC5640BLC4B, which offers 18 GHz input bandwidth and excellent broadband linearity, is used as an external master sampler at the front end of an ADC
The THA maintains excellent linearity over a very broad bandwidth with 56 dB or better Spurious Free Dynamic Range (SFDR) from DC to beyond 5 GHz at full scale input. Users may perform post conversion processing to reduce the wideband noise floor and may choose to tradeoff input signal level for higher linearity. A reduction of input level to half full scale results in 10-bit or better linearity across a wide bandwidth (Table 1)
Performance of the HMC5640BLC4B Track-and-Hold with a Commercially Available 1.6 GS/s, 12-Bit Dual ADC ######################################################################
As shown in Figure 3, the 18 GHz bandwidth HMC5640BLC4B radically enhances the sampling bandwidth well beyond the intrinsic 2.8 GHz ADC bandwidth. /predpolozitelno ADC -dual 12 bit National -smotri dannie nize / --------------------------------------------------------------------------
Comparison of the SFDR curves shows that the HMC5640BLC4B not only enhances the SFDR beyond the bandwidth of the ADC but also enhances it for frequencies within the 2.8 GHz ADC bandwidth by up to 11 dB.
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National Semiconductor Introduces Industry’s Fastest 12-bit ADC
Combination of 12-bit Resolution and 3.6-GSPS Sampling Rate Enables New Applications for Wideband Software-Defined Radios
May 24, 2010 – National Semiconductor Corp. (NYSE:NSM) today introduced the Industry’s fastest 12-bit analog-to-digital converter (ADC). At 3.6 Giga-samples per second (GSPS), the ADC12D1800 is 3.6 times faster than any other available 12-bit device. The ADC’s dynamic performance of -147 dBm/Hz noise floor, 52 dB noise power ratio (NPR) and -61 dBFS intermodulation distortion (IMD) enables a new generation of software-defined radio (SDR) architectures and applications.
In addition to the ADC12D1800, National introduced two other members of its ultra high-speed ADC family: the ADC12D1600 with sampling speed up to 3.2 GSPS and the ADC12D1000 with performance up to 2.0 GSPS. All three PowerWise® ADCs target wideband SDRs including radar, communications, multi-channel set-top box (STB), signal intelligence, and light detecting and ranging (LIDAR) applications https://www.national.com/news/item/0,1735,1459,00.html
Отправлено: 09.12.11 17:11. Заголовок: TI Bolsters Ultra-lo..
TI Bolsters Ultra-low Power, High Speed ADC Family Mon. July 25, 2011
Source: Texas Instruments Inc.
Texas Instruments Inc. expanded its line of high speed, ultra-low power consumption analog-to-digital converters (ADCs) with eight dual-channel devices available in 12- and 14-bit resolutions at speeds from 65 to 250 MSPS. With these additions, the ADS42xx family provides the performance and bandwidth needed for 3G/LTE wireless base stations, portable test and measurement and software defined radio applications, while providing best-in-class power consumption.
Key features and benefits of the ADS42xx family:
• The 14-bit ADS4246 uses 332 mW total power at 160 MSPS, 35-percent less power than its closest competitor. The family provides options down to 92 mW per channel to reduce board heating and operating costs.
• Pin-compatible 12- and 14-bit options, with speeds ranging from 65 to 250 MSPS, enable customers to move to higher resolutions and sample rates without redesigning the board.
• Pin-compatible with 11-bit, 200-MSPS ADS58C28, providing a license-free export option with up to 65 MHz of high-performance RF channel bandwidth at input frequencies over 200 MHz.
• 6-dB programmable gain option provides the flexibility needed to achieve a high signal-to-noise ratio of up to 73.6 decibel full scale (dBFS) and spurious free dynamic range (SFDR) of up to 91 dBc for high receive sensitivity in 3G/LTE wireless infrastructure.
TI offers a variety of tools and support to speed development with the ADS42xx family, including:
•An evaluation module (EVM) for each part.
•TSW1200 digital capture tool for rapid analysis of EVMs.
•An Altera-compatible high-speed mezzanine connector and Xilinx-compatible FPGA mezzanine connector, allowing ADS42xx EVMs to mate to FPGA EVMs to speed system-level prototyping.
•IBIS models to verify board signal integrity requirements.
•Software for calculation utilities, including an ADC harmonic calculator, anti-aliasing calculation tool, and jitter and SNR calculator.
High-speed ADC technology paves the way for software defined radio Yiannis N. Papantonopoulos, Systems and Applications Manager, Texas Instruments 8/3/2007 9:11 AM EDT Software Defined Radio (SDR) addresses the tremendous capital expenditure demands placed on operators as wireless standards continue to evolve and change. The cost to install infrastructure is considerable, and it's this cost that inhibits rapid adoption and deployment of new wireless technologies. This poses a significant hindrance to the agility of operators in offering new and improved services to their subscribers.
Paradoxically, the goal of a fully reconfigurable radio that can adapt to a new standard or accommodate multiple standards simply through software upgrades is not limited by software. Indeed, it is the analog domain and its bridge to the digital world that presents system designers with their biggest challenge. The focus of this article is on the challenges of analog-to-digital (A/D) conversion as they pertain to SDR implementations, and how breakthroughs in analog-to-digital converters (ADCs) can bring true SDR closer to reality.
The problem The big promise of SDR for operators is that it will eventually allow them to deploy one network, and one set of infrastructure capable of handling a broad range of radio frequencies and standards, along with their future evolutions. This requires the radio design to be flexible enough to allow for wider frequency coverage than usual. Additionally, it has to offer dynamic range beyond the range necessary for narrow band applications. So, ultimately, we could deal with a multi-carrier environment with carriers of different modulation types and bandwidths, blocking requirements, and other attributes.
Advances in digital signal processing (DSP) technology have elevated the digital backend capabilities of radios to levels that can be amenable to SDR implementations. Hence, the missing piece of the puzzle is getting the extremely-sensitive analog signals converted to the comfort of the digital domain. A/D conversion in these radios is pivotally important in trying to realize the goal. ADCs are used in both the receiver (Rx) and the transmitter (Tx) sections of the radio, and are the enabling components for SDR development
Key ADC specifications Among the primary specifications driving the design of the Rx section of the radio are sensitivity and usable bandwidth. In simple terms, sensitivity refers to the radio's ability to effectively process very low-level signals at the antenna input, expressed in dBm. For the ADC, this most commonly translates into signal-to-noise ratio (SNR) specifications expressed in dBc or dBFS (dBc is the ratio of signal to noise expressed in reference to the carrier, whereas dBFS refers back to the full scale input of the ADC).
Closely related to the radio's capability to receive small signals and reject larger interferers is the spurious-free dynamic range (SFDR) of the ADC. This is the ratio of the wanted signal (carrier) to the next highest spurious component in the ADC's output, whether it is harmonic or not, expressed in dBc. Finally, the usable bandwidth of the converter, a term really not specified effectively, deals with the actual signal bandwidth that the ADC can digitize with adequate SNR and SFDR performance.
In standard industry practice, ADCs are specified to their -3dB point of their analog input 'frequency response.' However, a lot of modern day converters show dramatically decreased performance as the analog input frequency increases past 200-300 MHz, even though their bandwidth is rated to several hundreds of MHz.
It's all about bandwidth One of the key advantages of SDR is its ability to handle a larger-than-usual frequency range without the need for new hardware. This is particularly appealing, given the nature of today's frequency map across the world. Each wireless standard has multiple frequencies defined for operation. For example, GSM alone can operate at frequencies around 400 MHz, 850 MHz, 900 MHz, 1800 MHz, 1900 MHz, and even 2500-2690 MHz for the GSM extension band. 3GPP frequencies include 1800 MHz, 1900 MHz and 2100 MHz, while WiMAX frequencies exist in the 2500 MHz, 3500 MHz, and all the way to 5 GHz, with more coming.
With such a plethora of frequencies, digitizing as large a signal bandwidth as possible through the ADC becomes a huge advantage. Therefore, it is the ADC sample rate that becomes critical in such implementations. ####################################################################
The Nyquist criterion limits the bandwidth an ADC can effectively digitize without aliasing (a process whereby the wanted signal after digitization folds over on itself thus producing distortion) to half its sample rate (Fs/2). Thus, for an ADC sampling at 200 MSPS (megasamples per second), the maximum bandwidth that can be effectively digitized is 100 MHz. In practical implementations, though, the filter used to band-limit the analog input to Fs/2 has a finite roll-off, which effectively further reduces the usable bandwidth. #####################################
Beyond the receiver, the demand for high bandwidth also is key for the transmit section of the radio. Since the cost of the power amplifier is proportional to its output power, a key method of reducing the overall bill-of-materials (BOM) and operational cost is through increasing its efficiency. Modern digital pre-distortion algorithms that linearize the power amplifier at the transmitter rely on feeding back to the digital processor a digitized bandwidth that is a multiple of the transmitted signal's bandwidth. This, in turn, necessitates the use of an ADC capable of sampling at very high rates.
Signal-to-noise ratio In order to maintain utmost sensitivity, an SDR design has to feature a large SNR so that very low-level received signals can be discerned, and effectively demodulated. The evolution of wireless standards to higher-order modulation schemes (such as 64QAM) imposes more stringent requirements on the SNR performance of the ADC. In situations where the received input power at the antenna is really low, the SNR of the ADC (in conjunction with the phase noise of the local oscillator) becomes the limiting factor and sets the sensitivity for the entire receiver.
Until recently, SDR designers had to trade off SNR for sample rate (bandwidth), since the state-of-the-art ADCs at several hundred MSPS were limited to resolution of 10 bits, with SNR levels around 50 dBFS. With the introduction of converters such as the ADS5463 (12-bit/500 MSPS), the envelope for monolithic 12-bit, ADCs essentially has doubled (previous art was at 250 MSPS). With SNR levels jumping to the mid-60s, implementations previously prohibitive can now become reality.
In addition to being able to effectively reconstruct as large an analog signal bandwidth as possible, the sample rate of the ADC offers an added benefit, usually referred to as processing gain. Typically, SNR for an ADC is calculated as the ratio of the power of the fundamental of a sinusoidal tone to the sum of the noise across the entire Nyquist band of the ADC (0 Hz through Fs/2, excluding DC). Typically, total noise is uniformly spread across the Nyquist zone. When the receiver processes a signal of a certain bandwidth within that zone, powerful digital filters can greatly attenuate the out-of-band noise. When the signal of interest has a bandwidth BWSIG and the ADC samples at a rate of Fs, the effective processing gain (PG) can be calculated as:
Figure 1 shows the processing gain that can be achieved by using a very high-speed ADC such as the ADS5463, sampling at 500 MSPS.
Figure 1: Processing gain versus wanted signal bandwidth for an ADC sampling at Fs = 500 MSPS (Click to enlarge image)
The power of the digital backend of the SDR can fully exploit the benefits of the wideband capabilities of the ADC.
Ultimately, the evolution of wireless receivers will entail direct sampling at the RF frequency. Although the ADC technology needed for such a task is not feasible today, it is not unreasonable to expect that eventually technological breakthroughs may enable it.
However, jitter needs to be taken into account since, ultimately, it will limit the SNR. The well-documented equation that relates SNR to jitter for a sampled system is given in Equation 2:
where fin represents the analog input frequency, and tjitter the RMS value of the system's jitter. The internal jitter of the ADC sampling circuitry is added (in a root of the sum of squares fashion) to the externally provided sampling clock to the ADC.
Note that the limitation of SNR is independent of the actual sampling frequency, but directly related to the analog input frequency. This fundamental limitation is a major design consideration when deciding the placement of the intermediate frequency (IF) in receiver design. The benefit of simplified Rx architecture and filtering (and, hence, reduced cost) is countered by the limitations imposed by jitter and clocking the ADC as the IF is increased.
Spurious-free dynamic range (SFDR) The linearity of an ADC, most often characterized by its SFDR, becomes critical in situations where the incident power at the receiver's antenna is of substantial power levels. This can happen when the wanted signal is strong (a desirable situation), or when an in-band interferer is strong (an undesirable situation).
In the latter case, the linearity of the ADC dictates whether the wanted signal can be effectively demodulated. This is particularly true when the desired signal's power is low. The presence of a large interferer effectively limits the application of any AGC function, since the total signal (wanted plus interferer) may already be approaching the full-scale range of the analog input. Thus, the ADC's inherent linearity performance becomes the bottleneck.
Just as jitter limits how high an SDR designer can place the IF, SFDR also weighs into that decision quite heavily. Many ADCs available in the market today exhibit high levels of linearity that are, however, limited to input frequencies below 200 MHz. Hence, the benefits of high IF placement cannot be realized due to the roll-off in SFDR performance.
New analog structures using cutting-edge BiCMOS process technologies have enabled the inclusion of an analog input buffer, capable of delivering high levels of SFDR across many hundreds of MHz. The analog input buffer of the ADS5463, for example, allows the user to easily achieve datasheet performance because it isolates the sensitive analog input from the switching within the ADC.
Additionally, it provides constant impedance across input frequency. Figure 2 shows that a converter such as the ADS5463 enables SFDR performance of over 70 dBc, for IFs at least as high as 500 MHz. ############################################################
Figure 1: ADS5463 SNR and SFDR performance over analog input frequency at 500 MSPS (Click to enlarge image)
This dramatic improvement in performance substantially simplifies the design of the radio, especially since it is coupled with very high levels of SNR and processing gain. Using a very-high input frequency can further reduce the cost of the radio, since it removes an extra down-conversion step and its associated BOM impact.
Conclusion The promise of true software-defined radio depends heavily on the evolution of high speed A/D conversion. Located at the heart of both the receiver and the transmitter, the ADC sets the performance for the entire radio. Recent breakthroughs in mixed-signal technology have enabled performance at unprecedented sample rates and analog input frequencies, simplifying the radio design and allowing for broader operating bandwidths and higher levels of sensitivity. As ADC technology keeps pushing the envelope, it will continue to pave the way for the advent of truly reconfigurable, multi-standard radio.
About the Author Yiannis Papantonopoulos is Systems and Applications manager for high-speed ADCs at Texas Instruments Inc. He can be reached at yiannis@ti.com.
E2V TECHNOLOGIES : e2v first to introduce 12bit 1.5 GSPS analogue to digital converter with both direct RF sampling in L-band and low input voltage range News Items
e2v first to introduce 12bit 1.5 GSPS analogue to digital converter with both direct RF sampling in L-band and low input voltage range date added : September 12, 2011
Building on the performance of its true single core high bandwidth family of ADCs with direct RF sampling, e2v announces the launch of
EV12AS200, a 12-bit 1.5 GSPS analogue to digital converter. #########################################
The new ADC combines the benefits of direct RF sampling up to L band, ##################################################
calibration free stable performance versus temperature and a wider choice of ADC input driving options, thanks to the lowest input voltage range on the market for 12bit GSPS ADCs.
This device enables further innovation in high verticality oscilloscopes, spectrum analysers, high dynamic range point-to-point microwave data links, electronic warfare systems and data acquisition COTS boards.
The EV12AS200 features a full power input bandwidth of 2.3GHz with a roll-off pattern optimised for operation in the L-band area. It also features the lowest input voltage range in the 12bit GSPS class with only 500mVp-p, without sacrificing performance in direct RF sampling. This delivers a significant reduction in distortion effects induced by high voltage swings at high frequencies in any amplifiers used prior to the ADC, such as variable gain amplifiers used for signal zooming purposes.
The low input voltage range of EV12AS200 is also a very convenient feature to build high verticality oscilloscopes with multiple amplification stages prior to the ADC while maintaining a very low level of distortion in the amplifiers.
EV12AS200 is also the only 12bit ADC operating at up to 1.5 GSPS without the use of any form of internal interleaving. ###############################################################################
! (ot awtora postinga) ###############
This is key for the EV12AS200 to achieve both a calibration-free stable dynamic performance versus temperature, and nominal dynamic performance that is available immediately at power-up as soon as the supply voltage has stabilised, without the need to wait for multi-second silicon warm-up and calibration.
Other noticeable benefits of EV12AS200 include a low latency of fewer than 5 clock cycles, which is convenient for real time systems, guaranteed no-missing codes at 1.5GSPS, important for high verticality oscilloscopes, an analogue and clock input impedance of 100 Ohms that is stable versus frequency and temperature, and fine adjustments of input gain and offset as well as clock skew, which facilitates interleaving of multiple converters to achieve even higher sample rates.
“This new ADC brings all the recognised benefits of e2v data converters familiar at 8 and 10 bit into the 12 bit GSPS class and enables further innovation in both direct RF sampling with stable performance at all temperatures and input driving flexibility. It also opens new possibilities for high resolution time domain applications such as high verticality oscilloscopes” said Nicolas Chantier, Product Marketing for e2v’s Broadband data conversion product line.
EV12AS200 is offered in a small footprint FpBGA 196 package with the choice of commercial temperature grade (0°C to +90°C) or industrial temperature grade (-40°C to +110°C).
Datasheet, samples and quotations are now available from e2v and from e2v’s authorised distributors around the world.
e2v is a leading global provider of specialist technology for high performance systems and equipment; delivering solutions, sub-systems and components for specialist applications within medical & science, aerospace & defence, and commercial & industrial markets.
e2v is headquartered in the UK, employs approximately 1500 people, has design and production facilities across Europe and North America, and has a global network of sales and technical support offices. For the year ended 31 March 2011, e2v reported sales of £229m and is listed on the London Stock Exchange. For more information visit e2v.com.
With over 20 years experience in the design and manufacture of advanced semiconductor components, e2v provides broadband data converters with high resolution (from 6 to 12 bits), high sampling rates (from 250 Msps to 5Gsps) and wide bandwidth (up to 5GHz)
e2v's family of 8, 10 and 12-bit A/D converters has grown to include sampling rates from 500 Msps to 5Gsps; all without the need for added off-chip external interleaving techniques.
e2v ADC's provide reveiver designers with market leading high linearity, ENOB and dynamic range coupled with analog bandwidths from 1GHz to over 3GHz for true high IF sampling.
Excellent noise and linearity up to and above fIN = 2.7 GHz Configurable to either 3.6 GSPS interleaved or 1800 MSPS dual ADC New DESCLKIQ Mode for high bandwidth, high sampling rate apps Pin-compatible with ADC1xD1x00, ADC12Dx00RF AutoSync feature for multi-chip synchronization Internally terminated, buffered, differential analog inputs Interleaved timing automatic and manual skew adjust Test patterns at output for system debug Time Stamp feature to capture external trigger Programmable gain, offset, and tAD adjust feature 1:1 non-demuxed or 1:2 demuxed LVDS outputs Applications
3G/4G Wireless Basestation
Receive Path DPD Path Wideband Microwave Backhaul RF Sampling Software Defined Radio Military Communications SIGINT RADAR / LIDAR Wideband Communications Consumer RF Test and Measurement
Отправлено: 12.12.11 17:05. Заголовок: Driving High Speed A..
Driving High Speed ADCs with the LMH6521 DVGA for High IF AC-Coupled Applications Texas Instruments Application Note 2195 Vong Philavanh November 16, 2011 Sampled data systems can be categorized into two main types. The first and simplest is the baseband system known as the “1st Nyquist-zone” system. The second is a more complex under-sampled system, often referred to as the subsampled system or Intermediate frequency (IF)-sampled system. ------------------ Baseband system applications are generally DCcoupled while the IF-sample systems applications tend to be AC-coupled. ----------------------------
In this application note, the LMH6521 is combined with National Semiconductor's high-speed analog-todigital convertor (ADC), the ADC16DV160, that is optimized for an IF frequency of 192 MHz.
17.2.1.1 Dual Edge Sampling Pin (DES) The Dual Edge Sampling (DES) Pin selects whether the ADC12D1800RF is in DES Mode (logic-high) or Non-DES Mode (logic-low). DES Mode means that a single analog input is sampled by both I- and Q-channels in a time-interleaved manner.
Отправлено: 22.12.11 21:58. Заголовок: The EV10AS150A combi..
The EV10AS150A combines a 10-bit 2.5 Gsps fully bipolar analog-to-digital converter chip, driving a fully bipolar DMUX chip with selectable Demultiplexing ratio (1:2) or (1:4). The 5 GHz full power input bandwidth of the ADC allows the direct digitization of up to 1 GHz broadband signals in the high IF region, in either L_Band or S_Band. ############################################################## The EV10AS150A features 7.8 effective bit and close to –58 dBFS spurious level at 2.5 Gsps over the full 1st Nyquist for large signals close to ADC Full Scale (–1 dBFS), and 8.1 bit ENOB at –6 dBFS in the 2nd Nyquist zone.
• 5 GHz Full Power Input Bandwidth (–3 dB) • ±0.5 dB Band Flatness from 10 MHz to 2.5 GHz • Input VSWR = 1.25:1 from DC to 2.5 GHz • Bit Error Rate: 10–12 at 2.5 Gsps
Отправлено: 28.12.11 13:14. Заголовок: e2v and SP Devices w..
e2v and SP Devices working together to deliver the ultimate in high-performance ADC solutions December 13, 2011 -- e2v and SP Devices today announced their collaboration in the provision of high-performance Analogue-to-Digital (ADC) solutions. With the unique combination of the market's fastest 12-bit ADC core speed from e2v, and cutting-edge digital post-processing technology from SP Devices, system designers now have access to never before seen ADC solutions.
This new resource is offered following market demand for more complete joined-up services to design teams. This solution from e2v and SP Devices provides an all-European ADC capability to deliver against designers' exacting requirements across a number of industries including test & measurement, military, and communications.
As an example, with their recently released EV12AS200, a 1.5 GSPS 12-bit ADC, e2v is introducing a true single-core device that, when combined with SP Devices ADX4 time-interleaving technology, enables 12-bit resolution at an unprecedented 6 GSPS. ####################################################################
"We are very excited about this collaboration with e2v", said Ulrik Lindblad, co-founder of SP Devices. "The combination of SP Devices' time-interleaving and linearization technology with e2v's impressive high-performance ADCs offers customers the ability to grow their business, stay ahead of competition, and enter new exciting markets."
"SP Devices' performance enhancing technologies and digitizers are well recognized in the industry," said Nicolas Chantier, Product Marketing Manager for e2v's broadband data converter group, adding "The key to achieving genuine performance breakthroughs in terms of resolution and sampling rate is precisely this unique combination of technology from e2v and SP Devices. Customers can now benefit from the coordinated support of both companies to reach the highest possible performance levels."
About e2v
e2v is a leading global provider of specialist technology for high performance systems and equipment; delivering solutions, sub-systems and components for specialist applications within medical & science, aerospace & defence, and commercial & industrial markets.
e2v is headquartered in the UK, employs approximately 1500 people, has design and production facilities across Europe and North America, and has a global network of sales and technical support offices. For the year ended 31 March 2011, e2v reported sales of Ј229m and is listed on the London Stock Exchange. For more information visit e2v.com.
About SP Devices
SP Devices (Signal Processing Devices Sweden AB and Signal Processing Devices Inc.) provides digital signal
processing IP for the enhancement of analogue-to-digital conversion and high speed digitizers. The IP products are available for implementation in ASICs or deployed on FPGA platforms. SP Devices' portfolio of products enables customers to build systems with state-of-the-art analogue-to-digital performance that enables advances in the areas of Test and Measurement, software defined radio, radio base station transceivers, digital imaging, high-speed data acquisition and broadband communication.
Additional company and product information is available at www.spdevices.com.
e2v and SP Devices working together to deliver the ultimate in high-performance ADC solutions date added : 12 December 2011
e2v and SP Devices today announced their collaboration in the provision of high-performance Analogue-to-Digital (ADC) solutions. With the unique combination of the market’s fastest 12-bit ADC core speed from e2v, and cutting-edge digital post-processing technology from SP Devices, system designers now have access to never before seen ADC solutions.
This new resource is offered following market demand for more complete joined-up services to design teams. This solution from e2v and SP Devices provides an all-European ADC capability to deliver against designers’ exacting requirements across a number of industries including test & measurement, military, and communications.
As an example, with their recently released EV12AS200, a 1.5 GSPS 12-bit ADC, e2v is introducing a true single-core device that, when combined with SP Devices ADX4 time-interleaving technology, enables 12-bit resolution at an unprecedented 6 GSPS.
“We are very excited about this collaboration with e2v”, said Ulrik Lindblad, co-founder of SP Devices. “The combination of SP Devices’ time-interleaving and linearization technology with e2v’s impressive high-performance ADCs offers customers the ability to grow their business, stay ahead of competition, and enter new exciting markets.”
“SP Devices’ performance enhancing technologies and digitizers are well recognized in the industry,” said Nicolas Chantier, Product Marketing Manager for e2v’s broadband data converter group, adding “The key to achieving genuine performance breakthroughs in terms of resolution and sampling rate is precisely this unique combination of technology from e2v and SP Devices. Customers can now benefit from the coordinated support of both companies to reach the highest possible performance levels.”
e2v is a leading global provider of specialist technology for high performance systems and equipment; delivering solutions, sub-systems and components for specialist applications within medical & science, aerospace & defence, and commercial & industrial markets.
e2v is headquartered in the UK, employs approximately 1500 people, has design and production facilities across Europe and North America, and has a global network of sales and technical support offices. For the year ended 31 March 2011, e2v reported sales of £229m and is listed on the London Stock Exchange. For more information visit e2v.com.
About SP Devices
SP Devices (Signal Processing Devices Sweden AB and Signal Processing Devices Inc.) provides digital signal
processing IP for the enhancement of analogue-to-digital conversion and high speed digitizers. The IP products are available for implementation in ASICs or deployed on FPGA platforms. SP Devices’ portfolio of products enables customers to build systems with state-of-the-art analogue-to-digital performance that enables advances in the areas of Test and Measurement, software defined radio, radio base station transceivers, digital imaging, high-speed data acquisition and broadband communication.
Additional company and product information is available at www.spdevices.com.
Отправлено: 28.12.11 17:11. Заголовок: TEK MICROSYSTEMS COM..
TEK MICROSYSTEMS COMBINES ULTRA HIGH SPEED ADC AND DAC WITH HIGHEST DENSITY FPGA PROCESSING 1 month 1 week ago → New Products The new Calypso-V6 Two or Six Channel 12-bit ADCs with Up To 3.6 GSPS per Channel The new Calypso-V6 Two or Six Channel 12-bit ADCs with Up To 3.6 GSPS per Channel (click image to zoom by 1.4x) The new Calypso-V6 Two or Six Channel 12-bit ADCs with Up To 3.6 GSPS per Channel The new Calypso-V6 Two or Six Channel 12-bit ADCs with Up To 3.6 GSPS per Channel (click image to zoom by 4.1x)
Washington, DC – November 15, 2011 – At the 48th Annual AOC International Symposium and Convention, TEK Microsystems, Incorporated, the leading supplier of VME and VXS-based signal acquisition, generation and FPGA-based processing products, has announced the latest member of our QuiXilica product family. The new Gemini-V6 supports either one 12-bit analog-to-digital converter (ADC) input channel at 3.6 GSPS (Gigasamples per second) or three input channels at 1.8 GSPS, combined with a 12-bit DAC output channel operating at up to 4.0 GSPS. Like all members of the QuiXilica-V6 VME / VXS family, the Gemini-V6 is compatible with legacy VME systems as well as newer ANSI/VITA 41 VXS based systems and combines the highest density FPGA processing available in any 6U form factor with the ultimate in ultra wide band ADC signal acquisition and DAC signal generation for advanced Electronic Warfare applications.
“Tekmicro is committed to providing our customers with the best available ADC and DAC technology for 10, 12, and 16 bit resolutions. The new Gemini-V6 is another industry first for Tekmicro, combining the fastest available sampling rate for 12-bit signal acquisition with a 4 GHz DAC signal output in a 6U VME / VXS form factor”, comments Andrew Reddig, President / CTO of Tekmicro. “By integrating ultra high speed ADC and DAC technology with high density FPGA processing, we are able to meet our customers’ requests for a modular COTS building block with ultra low input-to-output latency, enabling the most advanced DRFM-based EW applications.”
Gemini-V6 Supports Ultra Wide Band Signal Acquisition and Generation
Gemini-V6 is based on the National Semiconductor ADC12D1800RF device which supports either a pair of channels in non-interleaved mode or a single channel using 2:1 interleaved sampling. Gemini-V6 contains two ADC devices, supporting a total of either three channels plus trigger at 1.8 GSPS or one channels plus trigger at 3.6 GSPS, plus a separate 12-bit DAC output channel based on the Euvis M653D which operates at up to 4.0 GSPS.
Gemini-V6 also includes sample-accurate trigger synchronization in all modes, allowing synchronization of input and output channels as well as coherent processing for N-channel algorithms both within a single card and across multiple cards. GPS and timestamp inputs are also available to support precise timing and geolocation.
High Density FPGA Processing
The Gemini-V6 contains two front end FPGA devices, one attached to the ADCs and one to the DAC. The front end FPGAs can be configured with LX240, SX315, or SX475 devices, providing both the highest FPGA processing density available in any 6U form factor today as well as the only VME / VXS platform supporting Virtex-6 FPGAs.
The two front end FPGAs are supplemented with a “backend” FPGA which can be used for additional processing or for backplane or front panel communications. The backend FPGA can also be configured with a range of Xilinx Virtex-6 FPGA options, from the standard LX240 up to a SX475, depending on application requirements.
Memory, Network and Interconnect Resources
The Gemini-V6 includes six banks of DDR3 memory with total capacity of 5 GB and aggregate throughput of 32 GB/s, supporting a wide range of signal processing algorithms with deep memory buffering of the entire signal acquisition stream. The backend FPGA also has two banks of QDR-II memory available for applications that require memory with lower random access latency. Each FPGA supports a Gigabit Ethernet interface for control plane purposes, along with a range of front panel and backplane I/O connections for high speed communications with other processing cards. Gemini-V6 provides an onboard Gigabit Ethernet switch for network connectivity between the front panel, backplane interface, and all onboard FPGAs.
System Management
The Gemini-V6 is based on Tekmicro’s QuiXilica-V6 baseboard which provides the tools necessary for reliability, availability and maintainability in deployed applications. A dedicated system management processor can be used to monitor power and thermal sensors, and is also responsible for managing FPGA initialization and bitstream management. Tekmicro’s QuiXstart technology, included in QuiXilica products since 2005, supports FPGA bitstreams using either onboard flash memory or offboard network resources to support secure applications while maintaining hardware in a sanitized state.
Ruggedization Support for Deployed Applications
The Gemini-V6 is available for a wide range of operating environments, including commercial grade, rugged air and conduction cooled, allowing the card to be used for both laboratory and deployed requirements in both VME and VXS systems.
Comprehensive Developers Kit Speeds Time To Market
The Gemini-V6 is supported by a comprehensive Developer’s Kit that includes interface IP cores for all onboard resources along with Tekmicro’s QuiXtream network toolkit for rapid application development using network-enabled FPGAs. Reference designs are included, with source code, to support quick prototyping of user applications with minimal learning curve.
The Gemini-V6 will be available in for early access customers starting in January 2012.
About TEK Microsystems, Incorporated.
Founded in 1981 and headquartered in Chelmsford, Massachusetts, Tekmicro designs, manufactures and delivers a wide range of advanced high-performance boards and systems for embedded real-time signal acquisition, generation, processing, storage and recording. Tekmicro provides both commercial and rugged grade products which are used in real-time systems designed for a wide range of defense, intelligence and industrial applications such as C4ISR, signals intelligence, electronic warfare and radar. For additional information see www.tekmicro.com. Source: TEK Microsystems Inc
Отправлено: 28.12.11 17:30. Заголовок: FORM B - PROPOSAL SU..
FORM B - PROPOSAL SUMMARY PROPOSAL NUMBER: 09-2 S1.02-9911 PHASE 1 CONTRACT NUMBER: NNX10CD96P SUBTOPIC TITLE: Active Microwave Technologies PROPOSAL TITLE: High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems
SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone) Ridgetop Group, Inc. 6595 North Oracle Road Tucson, AZ 85704 - 5645 (520) 742-3300
PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone) Justin Judkins justin.judkins@ridgetopgroup.com 6595 North Oracle Road Tucson, AZ 85704 - 5645 (520) 742-3300
Estimated Technology Readiness Level (TRL) at beginning and end of contract: Begin: 4 End: 8
TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words) In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming (DBF) systems that will be used in NASA's future radar applications. The ADC will employ a novel combination of time interleaving, high-speed silicon-germanium BiCMOS technology and low-power techniques, such as the double-sampling technique, providing exceptional sampling speed of 500 MSPS, 1.5 GHz analog bandwidth,12 bits of resolution, and below 500 mW power dissipation, exceeding NASA's requirements. Ordinarily, ADC design requires large trade-offs in speed, resolution, and power consumption. The significance of this innovation is that it simultaneously provides a high-speed, high-resolution, and low-power ADC that is well ahead of the state of the art. These three characteristics are needed for DBF systems that contain large ADC arrays. The power consumption of existing ADC chips prohibits implementation of large DBF arrays in space. Ridgetop's innovative design leverages newer semiconductor process technologies that combine silicon and germanium into a compound semiconductor. Ridgetop has identified two Phase 2 objectives, which are: 1. Design, fabricate and characterize Test Chip 1 that contains critical ADC subcircuits. 2. Design, fabricate and characterize Test Chip 2 that contains the complete radiation tolerant, digitally calibrated, time-interleaved ADC design. During Phase 1 Ridgetop identified the topologies for all of the circuit blocks that will be included on Test Chip 1 and Test Chip 2. Ridgetop has also completed transistor-level designs for the key components on these chips. Estimated TRL at beginning and end of Phase 2 contract: Begin 4; End 8.
POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words) NASA applications include radar, imaging, detectors, space radio astronomy, and communication circuits. Space radar systems stand to benefit from the combination of high resolution and low power of the proposed ADC. The technology is ideal for NASA Jet Propulsion Laboratory's radar research program, UAVSAR program, and many other critical communication circuits.
POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words) Non-NASA commercial applications include: В• Phased arrays for ballistic missile defense (BMD) (the DBF technology is commonly cited as a "huge leap" for radar-based missile defense systems) В• Space-based radar for military/intelligence targets or earthquake detection В• Measurement applications, including pin test electronics on ATE systems В• Space navigation systems В• Conformal arrays for UAVs В• Telecommunications applications, such as software-defined radio В• Medical imaging device manufacturers В• Computer networks, hard disk readout circuits, digital oscilloscopes, etc. ; these applications require 500 MSPS sampling speeds, and the "effective number of bits" (ENOB) used in contemporary converters is <10 bits, and the power dissipation is >2 W В• Power-limited applications, such as laptops, wireless devices and PDAs.
TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.) Guidance, Navigation, and Control Microwave/Submillimeter Radiation-Hard/Resistant Electronics Telemetry, Tracking and Control Form Generated on 08-06-10 17:29
Отправлено: 28.12.11 17:30. Заголовок: FORM B - PROPOSAL SU..
FORM B - PROPOSAL SUMMARY PROPOSAL NUMBER: 09-2 S1.02-9911 PHASE 1 CONTRACT NUMBER: NNX10CD96P SUBTOPIC TITLE: Active Microwave Technologies PROPOSAL TITLE: High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems
SMALL BUSINESS CONCERN (Firm Name, Mail Address, City/State/Zip, Phone) Ridgetop Group, Inc. 6595 North Oracle Road Tucson, AZ 85704 - 5645 (520) 742-3300
PRINCIPAL INVESTIGATOR/PROJECT MANAGER (Name, E-mail, Mail Address, City/State/Zip, Phone) Justin Judkins justin.judkins@ridgetopgroup.com 6595 North Oracle Road Tucson, AZ 85704 - 5645 (520) 742-3300
Estimated Technology Readiness Level (TRL) at beginning and end of contract: Begin: 4 End: 8
TECHNICAL ABSTRACT (Limit 2000 characters, approximately 200 words) In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming (DBF) systems that will be used in NASA's future radar applications. The ADC will employ a novel combination of time interleaving, high-speed silicon-germanium BiCMOS technology and low-power techniques, such as the double-sampling technique, providing exceptional sampling speed of 500 MSPS, 1.5 GHz analog bandwidth,12 bits of resolution, and below 500 mW power dissipation, exceeding NASA's requirements. Ordinarily, ADC design requires large trade-offs in speed, resolution, and power consumption. The significance of this innovation is that it simultaneously provides a high-speed, high-resolution, and low-power ADC that is well ahead of the state of the art. These three characteristics are needed for DBF systems that contain large ADC arrays. The power consumption of existing ADC chips prohibits implementation of large DBF arrays in space. Ridgetop's innovative design leverages newer semiconductor process technologies that combine silicon and germanium into a compound semiconductor. Ridgetop has identified two Phase 2 objectives, which are: 1. Design, fabricate and characterize Test Chip 1 that contains critical ADC subcircuits. 2. Design, fabricate and characterize Test Chip 2 that contains the complete radiation tolerant, digitally calibrated, time-interleaved ADC design. During Phase 1 Ridgetop identified the topologies for all of the circuit blocks that will be included on Test Chip 1 and Test Chip 2. Ridgetop has also completed transistor-level designs for the key components on these chips. Estimated TRL at beginning and end of Phase 2 contract: Begin 4; End 8.
POTENTIAL NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words) NASA applications include radar, imaging, detectors, space radio astronomy, and communication circuits. Space radar systems stand to benefit from the combination of high resolution and low power of the proposed ADC. The technology is ideal for NASA Jet Propulsion Laboratory's radar research program, UAVSAR program, and many other critical communication circuits.
POTENTIAL NON-NASA COMMERCIAL APPLICATIONS (Limit 1500 characters, approximately 150 words) Non-NASA commercial applications include: В• Phased arrays for ballistic missile defense (BMD) (the DBF technology is commonly cited as a "huge leap" for radar-based missile defense systems) В• Space-based radar for military/intelligence targets or earthquake detection В• Measurement applications, including pin test electronics on ATE systems В• Space navigation systems В• Conformal arrays for UAVs В• Telecommunications applications, such as software-defined radio В• Medical imaging device manufacturers В• Computer networks, hard disk readout circuits, digital oscilloscopes, etc. ; these applications require 500 MSPS sampling speeds, and the "effective number of bits" (ENOB) used in contemporary converters is <10 bits, and the power dissipation is >2 W В• Power-limited applications, such as laptops, wireless devices and PDAs.
TECHNOLOGY TAXONOMY MAPPING (NASA's technology taxonomy has been developed by the SBIR-STTR program to disseminate awareness of proposed and awarded R/R&D in the agency. It is a listing of over 100 technologies, sorted into broad categories, of interest to NASA.) Guidance, Navigation, and Control Microwave/Submillimeter Radiation-Hard/Resistant Electronics Telemetry, Tracking and Control Form Generated on 08-06-10 17:29
The ECHO design utilized the Astrium spacecraft bus, had a baseline antenna size of 2 m x 13.8 m, and was designed to fit within the Dnepr launch vehicle fairing. To increase the performance margin the InSAR mission is baselining a larger SAR antenna compared to ECHO. The Spectrum Astro SA-200HP bus was examined for the InSAR mission. The resulting preliminary Flight System configuration included accommodation of the larger (2.5 m x 13.8 m) InSAR antenna and met the Delta II 2920-10 payload fairing volume constraints. The Ball Aerospace BCP 2000 bus was also examined for the InSAR mission. This configuration included the larger SAR antenna (2.5 m x 13.8 m) and preliminary analysis indicates the design can meet the Delta II 2920-10 payload fairing volume constraints. Previous studies and the InSAR industry survey effort give high confidence in the ability to accommodate the InSAR payload on a commercial spacecraft bus.
str 51/62 ########### 4.10.2 L-band Transceiver The L-band Transceiver takes the IF chirp generated at 142.5 – 222.5 MHz and upconverts it to L-band (1220 – 1300 MHz) with a local oscillator of 1440 MHz (thus inverting the spectrum). Using this high-side LO mixing scheme produces no mixing intermodulation products in the L -band chirp. In the Receive chain, it is desirable to avoid requiring very sharp filters since they are more sensitive to phase vs. temperature variations, and are more bulky. So, the L-band filter is generous and its purpose is to only limit possible interference and noise into the receiver. With an LO of 1320 MHz (again inverting the spectrum) the resulting baseband frequency range of 22.5 to 102.5 We chose an offset video frequency range of 22.5MHz to 102.5MHz to be digitized at 250MSps
The ECHO design utilized the Astrium spacecraft bus, had a baseline antenna size of 2 m x 13.8 m, and was designed to fit within the Dnepr launch vehicle fairing. To increase the performance margin the InSAR mission is baselining a larger SAR antenna compared to ECHO. The Spectrum Astro SA-200HP bus was examined for the InSAR mission. The resulting preliminary Flight System configuration included accommodation of the larger (2.5 m x 13.8 m) InSAR antenna and met the Delta II 2920-10 payload fairing volume constraints. The Ball Aerospace BCP 2000 bus was also examined for the InSAR mission. This configuration included the larger SAR antenna (2.5 m x 13.8 m) and preliminary analysis indicates the design can meet the Delta II 2920-10 payload fairing volume constraints. Previous studies and the InSAR industry survey effort give high confidence in the ability to accommodate the InSAR payload on a commercial spacecraft bus.
str 51/62 ########### 4.10.2 L-band Transceiver The L-band Transceiver takes the IF chirp generated at 142.5 – 222.5 MHz and upconverts it to L-band (1220 – 1300 MHz) with a local oscillator of 1440 MHz (thus inverting the spectrum). Using this high-side LO mixing scheme produces no mixing intermodulation products in the L -band chirp. In the Receive chain, it is desirable to avoid requiring very sharp filters since they are more sensitive to phase vs. temperature variations, and are more bulky. So, the L-band filter is generous and its purpose is to only limit possible interference and noise into the receiver. With an LO of 1320 MHz (again inverting the spectrum) the resulting baseband frequency range of 22.5 to 102.5 We chose an offset video frequency range of 22.5MHz to 102.5MHz to be digitized at 250MSps
4.11.2 Science Acquisition ADC A high sampling rate ADC (Analog-to-Digital Converter) was investigated for conversion of the analog offset video receive signal into a digital stream. The goal was to identify a fairly high speed, low power ADC for InSAR science data acquisition. A minimum sampling rate of 250 MHz is required to sufficiently sample the bandwidth.
80 mgz
T.e . po treb .NASA esli ADC emeet 1.5 GSPS to polosa signala mozet bit maximum 500 mgz ############################################################## nachalnaya w PRO/BMDO Lincoln laboratory C-band radar
Отправлено: 28.12.11 18:28. Заголовок: Digital intermediate..
Digital intermediate frequency receiver module for use in airborne SAR applications Assignee: Sandia Corporation (Albuquerque, NM) ---------------------------------------------------------
BACKGROUND
Fine-resolution, high-performance synthetic aperture radar (SAR) system having real-time image formation capabilities are currently being developed. For example, a system being developed by Sandia National Laboratories has a 4 GHz first intermediate frequency (IF) receiver. A simplified block diagram of the current generation IF receiver is shown in FIG. 1 which has been labeled as prior art.
1. A digital receiver for use in radar systems, comprising: an intermediate frequency (IF) converter to translate a higher frequency 1st IF to a lower frequency 2nd IF; an analog-to-digital converter (ADC); a digital signal processor (DSP) including IF (range) domain and Doppler (azimuth) domain filtering, and at least one phase history data interface; wherein the IF converter translates a given radar 1st IF frequency to a 2nd IF necessary to facilitate sampling and efficient quadrature demodulation, and at least one phase history output interface moves data to an image formation processor or a raw phase history storage subsystem.
5. The invention of claim 1 wherein said second IF frequency is one fourth of the ADC sample frequency. (MAX108 1 gsps) 20. The invention of claim 1 wherein the first IF is at about 4 GHz and the second IF frequency is at about 250 MHz.
The AF202 is fully supported on ApisSys 3U VPX FPGA processing engines, making it ideally suited for test and measurement, Electronic Warfare, Ultra Wideband Radar Receivers or LIDAR applications.
ADC Dynamic Considerations Selecting the Drive Amplifier Based on ADC Dynamic Performance Driving Flash Converters Driving the AD9050 Single-Supply ADC Driving ADCs with Switched Capacitor Inputs Gain Setting and Level Shifting External Reference Voltage Generation ADC Input Protection and Clamping Applications for Clamping Amplifiers Noise Consideratio
Отправлено: 28.12.11 20:19. Заголовок: As in many communica..
As in many communications applications, the defense-electronics industry has been trending toward receivers with more bandwidth and higher dynamic range. Applications in this segment include Signals Intelligence (SIGINT) receivers, as well as radar for military and Homeland Security usage. SIGINT systems can be classified as Communications Intelligence (COMINT, communication between people) or Electronic Intelligence (ELINT, typically radar signals).
Both COMINT and ELINT systems benefit from higher bandwidth, since more information is gathered in a given amount of time. Higher bandwidth in a radar receiver produces greater spatial resolution, which in turn creates the ability to distinguish smaller targets or multiple targets that are clustered together. --------------
Traditionally, 100-200 MSPS high-resolution ADCs have been used in SIGINT and radar receivers. More recently, these systems have employed 12-14 bit converters with sample rates in the 250-500 MSPS range. Current developments are requiring multi-GSPS converters in this same resolution range, which favors time interleaving of multiple monolithic ADCs on the printed circuit board. In this application, the power consumption of each ADC is critical, since some radar receivers may use hundreds of ADCs.
A second trend in defense electronics receivers is toward higher dynamic range, which is predominantly set by the SNR. ---------------------------------------------------------------------------------------------------------------------------------------- Dynamic range defines the receiver’s ability to detect small signals in the presence of large signals.
For example, consider two objects being imaged by a radar system in which the target is further from the antenna than a second object. The closest object will produce the strongest backscatter signal, thereby determining the total gain that can be applied without saturating the receiver. The target signal will be much smaller, and may not be received at all if its magnitude is below the detection threshold set by the dynamic range.
In SIGINT systems, higher dynamic range translates to successful capture and decoding of weaker or more distant signals in the presence of interference (either natural or man-made), thereby providing more advanced warning of threats. A low power, high SNR, 14-bit, 500 MSPS ADC, such as the ISLA214P50IRZ from Intersil -- with built-in support for time-interleaved systems -- is an enabling technology for the defense electronics industry, especially SIGINT and radar.
Отправлено: 28.12.11 20:35. Заголовок: Another benefit of s..
Another benefit of sampling at higher frequencies is that in systems where large bandwidths are not required, the high-IF sampling of the faster converters can be used to gain SNR performance using of decimation. When decimating an A/D converter's output, you essentially throw away a periodic number of samples. Every time the output is decimated by a factor of two, where half the samples are removed, the SNR is improved by three dB. The cost is that the effective sample rate is now halved and, therefore, so is the available bandwidth.
For example, suppose a system requires only 20 MHz of bandwidth, but the form factor needs to be small. It is possible with today's fastest 14-bit A/D converter to sample this 20 MHz of bandwidth at 200 MSPS with the center input frequency being 350 MHz, a reasonable output for an RF-to-IF mixing stage. Choosing this frequency for the IF centers the signal band in the converter's Nyquist zone, which spans 300 to 400 MHz. With the signal bandwidth residing in the 340-360 MHz range, the AAF has 40 MHz on either side of the signal to operate. From the contour plots in Figure 1, a converter can achieve 69 dBFS SNR and 73 dBc SFDR at this sample rate and input frequency.
With only 20 MHz of bandwidth to sample, a DDC's numerically controlled oscillator (NCO) could mix the signal to the I and Q bands. In turn, this allows the 200 MSPS sample rate to be decimated by a factor of four to an effective sample rate of 50 MSPS, increasing the SNR by 6 dB to 75 dBFS.
Dual Channel Gain-Ranging ADC with RSSI: AD6600 Optimized for “Narrowband”, IF-Sampling Receivers Sampling to 20 MSPS; digitizes Analog inputs to 70- 250 MHz 90+ dB Dynamic Range: 30 dB variable attenuation & 60+ dB in ADC
60+ dB in ADC
chto malo ...s ARU terjaetsja slabij signal #############################
2.0 Features Key Features of the SP16160CH1RB High-IF Sub-Sampling Receiver Reference Design Board Ўц Demonstrates a high-IF sub-sampling subsystem architecture used in wireless infrastructure systems Ўц Configured for a 20 MHz input bandwidth centered at 192 MHz Ўц Configured with a low-noise, 153.6 MSPS CMOS sampling clock Ўц Featured Products Include: ЎЄ ADC16DV160 dual 16-bit, 160 Megasample per second (MSPS) ADC with parallel LVDS outputs ЎЄ LMH6517 Digitally-controlled, Variable Gain Amplifier (DVGA) with 31.5 dB gain range in 0.5 dB steps ЎЄ LMK04031B low-jitter precision clock conditioner consisting of cascaded phase locked loops (PLLs), an internal voltage controlled oscillator (VCO) and a distribution stage ЎЄ Several energy-efficient power management ICs Ўц Large-signal (-1 dBFS) performance for a 192 MHz input signal: ЎЄ SNR = 71 dBFS ЎЄ SFDR > 80 dBFS Ўц Small-signal (-6 dBFS) performance for a 192 MHz input signal: ЎЄ SNR = 72.7 dBFS ЎЄ SFDR > 92 dBFS Ўц 200 kHz channel performance for base-station receiver applications: ЎЄ SNR = 99 dBFS under normal conditions ЎЄ SNR = 94 dBFS under blocking conditions ЎЄ SFDR > 90dBFS under blocking conditions Ўц Total integrated jitter < 200 fs
Отправлено: 30.12.11 00:42. Заголовок: JPL 2010 I. Introd..
JPL 2010
I. Introduction To address the future telemetry, navigation, and radio science needs of the Deep Space Network (DSN), considerable e ort at JPL has been directed toward the development of a wideband ground receiver, intended to supplement and expand the capabilities of the currently operational Block V Receiver (BVR). Among the challenges encountered in this e ort has been the need to process both high data rate telemetry (well in excess of 150 Mbps), as well as telemetry from very low-rate missions. Another key element of this work has been the selection of a processing platform that is well-suited to rmware and software recon gurability. These objectives have led to the development of the Recon gurable Wideband Ground Receiver (RWGR): a variable data rate,
The RWGR is an intermediate frequency (IF) sampling receiver that operates at a xed input sampling rate of 1:28 GHz. It is designed to accommodate a continuous range of data rates from 4 Bd (symbols/second or baud) #########################################################
to 320 MBd, and is capable of processing 500 MHz of bandwidth. ########################################
In contrast, the BVR operates at a sample rate of 160 MHz and can only accommodate a bandwidth of 72 MHz.
Отправлено: 30.12.11 18:20. Заголовок: This article shows h..
This article shows how averaging the outputs of multiple high-speed ADCs can be used to improve data converter SNR. While an alternate technique of oversampling the input signal using faster ADCs is possible, the averaging approach seems preferable because faster ADCs which enable oversampling may not be available, and lower-speed ADCs used in an averaging approach may have better initial SNR specifications and lower power. This article examined the averaging approach.
Hardware was built to measure the SNR performance of using two and three high-speed (190 Msps) ADCs to sample an input signal in parallel. We found that special care must be given to the impedance transformation of the input matching circuit, as a lot of signal attenuation and distortion can be caused by the impedance mismatch.
To perform these complex functions, the MDR digital processing subsystem relies on 14 custom application-specific integrated circuits and 397 large-scale integrated (LSI) circuits, all fabricated in CMOS technology. This figure represents a decrease of 37 percent from the 630 custom LSI circuits required for each LDR payload.
1 IF (pch) = 7.4 ghz 2. IF verojatno ot 70 mhz do 280 mgz
t.e. vozmozno ispolzowanie 16 bit ADC s SNR na 70 mgz 80 db LTC 2217/16/15 Linear technology
ili AD9467 200/250 msps i 73-74 db SNR na 170 -280 mgz
Radio Frequency Subsystem (RFSS) The RF subsystem includes the processing and receiving components and the downlink group. The processing and receive group performs the following four payload functions:
amplifies, dehops, and downconverts the EHF waveform to the first intermediate frequency (IF) via the low-noise amplifier/downconverter; receives, amplifies, downconverts, and switches the first IF to the second IF for input to one of four demodulator groups of eight channels each; employs a differential phase shift key (DPSK) to modulate and upconvert onto a hopped SHF carrier for input to the downlink group; and generates and distributes the hopping and fixed local oscillators for the antenna coverage subsystem, digital subsystem and RFSS. The downlink group amplifies, filters and switches, on a hop-by-hop basis, the SHF waveform to any of the eight antennas. The SHF amplifiers are triple-redundant traveling wave tube amplifiers. Switching capability is provided by a high speed/high power beam select switch.
With the MDR payload, Milstar 6 is capable of processing data at speeds up to 1.5 megabits per second. With the LDR payload, the satellite can transmit voice and data at 75 to 2400 bits per second. After testing and systems evaluation, the $800 million Milstar 6 ##################
T.e. bez NIOKR podobnij sputnik segodnja budet stoit segodnja bolee 1 mlrd $ za 1
is expected to be fully operational within two months and will aid military forces worldwide by ensuring critical information reaches its destination quickly and securely. The Milstar 6 satellite is expected to last at least ten years.
Each Milstar satellite weighs about 10,000 pounds and can be described as a "switchboard" in space, directing the traffic it receives from terminal to terminal anywhere on Earth
Отправлено: 30.12.11 21:30. Заголовок: David A. DeBell and ..
David A. DeBell and Thomas S. Diviney
Northrop Grumman Corp. (USA) ------------------------------------------ IF (intermediate frequency) sampling is a method of sampling the received radar waveform out of the IF channel directly, without mixing to baseband, using a single A/D converter. ------------------------------------- The sampling rate needed is a multiple of the bandwidth of the IF filter, of the order of 3 times the -3 dB bandwidth. -------------------------------------------------------------------------------------------------------------------------------- IF filter skirt attenuation limits aliasing effects and permits apparent undersampling of the IF frequency.
Stretch processing is the method of matching the radar's LO frequency ramp rate (linear FM) to the transmit waveform's `chirp', in order to limit the IF bandwidth requirement to a value much less than the RF bandwidth and thus permit a lower rate of sampling. ----------------------------------------------------------------------------------------------------------------------------------------------------------- The combination of IF sampling and stretch processing is advantageous because A/D samplers are now able to operate at adequately short sample- and-hold aperture times, for use at IF frequencies, with a good number of bits resolution, and stretch processing can use narrow IF bandwidths. ------------------------------------------------------------------------------------------------------------------------------------------------------------------- Therefore, high range resolution can be achieved at a lower cost than with quadrature channels at baseband and dual A/D's. Added benefits are the elimination of I-Q imbalance effects, A/D DC offset effects, and the need for calibration of these effects. Some A/D saturation can also be tolerated. A Fast Fourier Transform of the real sample data set is easily converted to an inphase and quadrature output data set for further operations. The paper goes into the equations and methodology of such a radar system and delineates the hardware differences between the baseband approach and the IF sampling approach.
Stretch processing relieves the signal processor bandwidth problem by giving up all-range processing to obtain a narrow-band signal processor. If we were to use a matched filter we could look for targets over the entire waveform pulse repetition interval (PRI). With stretch processing we are limited to a range extent that is usually smaller than an uncompressed pulse width.
Thus, we couldn’t use stretch processing for search because search requires looking for targets over a large range extent, usually many pulse widths long. --------------------------------------- We could use stretch processing for track because we already know range fairly well but want a more accurate measurement of it. ------------------------------------------------------------------------------------------------------------------------------------------------------- We must point out that, in general, wide bandwidth waveforms, and thus the need for stretch processing, is “overkill” for tracking. Generally speaking, bandwidths of 1s to 10s of MHz are sufficient for tracking --------------------------------------------------------------
One of the most common uses of wide bandwidth waveforms, and stretch processing, is in discrimination, where we need to distinguish individual scatterers on a target. Another use we will look at is in SAR (synthetic aperture radar). Here we only try to map a small range extent of the ground but want very good range resolution to distinguish the individual scatterers that constitute the scene.
Thus, the stretch processor encounters a SNR loss of h T relative to the matched filter. This means that we should be careful about using stretch processing for range extents that are significantly longer of the transmit pulse width. At first inspection it appears as if stretch processing could offer better SNR than a matched filter, which would contradict the fact that the matched filter maximizes SNR. This apparent contradiction is resolved by the stretch processor constraint imposed by Eqution (15). Specifically, h R T . The constraint if Equation (42) also demonstrates another reason why stretch processing should not be used in a search function: it would be too lossy.
We will assume base-band processing in these discussions. In practice the mixer output will be at some intermediate frequency (IF). The signal could be brought to base-band using a synchronous detector or, as in some modern radars, by using IF sampling (i.e. a digital receiver). In either case, the effective ADC rate (the sample rate of the complex, digital base-band signal) will be as derived here
Specifically, we consider a waveform with a bandwidth of 500 MHz and a pulse width of 100 μs. We assume further that the matched filter is matched to the target Doppler. That is, d M f f . For the first case we consider a typical aircraft range-rate of -150 m/s and for the second case we consider a ballistic missile with a (extreme) range-rate of -7500 m/s. Plots of the matched filter outputs for the two cases are shown in Figure 5 and Figure 6.
Отправлено: 30.12.11 21:45. Заголовок: The ARPA-Lincoln C-b..
The ARPA-Lincoln C-band Observables Radar, or ALCOR [20], on Roi-Namur, Kwajalein Atoll, Marshall Islands, had a wideband (512 MHz) 10-μseclong linear-FM transmitted-pulse waveform (see the article entitled “Wideband Radar for Ballistic Missile Defense and Range-Doppler Imaging of Satellites,” by William W. Camp et al., in this issue). ALCOR was a key tool in developing discrimination techniques for ballistic missile defense. The wide bandwidth yielded a range resolution that could resolve individual scatterers on reentering warhead-like objects. This waveform was normally processed with the STRETCH technique, which is a clever time-bandwidth exchange process developed by the Airborne Instrument Laboratory [21, 22].
mixed with a linear-FM chirp and the low-frequency sideband is Fourier transformed to yield range information. For a variety of reasons, the output bandwidth and consequently the range window were limited. For example, the ALCOR STRETCH processor yielded only a thirty-meter data window. Therefore, examination of a number of reentry objects, or the long ionized trails or wakes behind some objects, required a sequence of transmissions.
Отправлено: 30.12.11 21:48. Заголовок: This sequential appr..
This sequential approach was inadequate in dealing with the challenging discrimination tasks posed by reentry complexes, which consist not only of the reentry vehicle, but also a large number of other objects, including tank debris and decoys, spread out over an extended range interval. What was needed was a signal processor capable of performing pulse compression over a large range interval on each pulse. Lincoln Laboratory contracted with Hazeltine Laboratory to develop a 512-MHz-bandwidth all-range analog pulse compressor employing
thirty-two parallel narrowband dispersive bridged-T networks built ############################################
out of lumped components, to cover the bandwidth. The resulting processing unit, shown in Figure 3, was large (it filled about seven relay racks) and complex, and it required a great deal of tweaking to yield reasonable sidelobes.
During 1972 and 1973, Lincoln Laboratory developed a 512-MHz-bandwidth (on a 1-GHz intermediate frequency [IF]) 10-μsec RAC linear-FM pulse compressor [23].
Waveform Variations by Mode.Although the specific waveform is hard to pre-
dict, typical waveform variations can be tabulated based on observed behavior of a number of existing A-S radar systems. Table 5.1 shows the range of parameters that can be observed as a function of radar mode. The parameter ranges listed are PRF, pulse width, duty cycle, pulse compression ratio, independent frequency looks, pulses per coherent processing interval (CPI), transmitted bandwidth, and total pulses in a Time-On-Target (TOT).
Obviously, most radars do not contain all of this variation, but modes exist in many fighter aircraft, which represent a good fraction of the parameter range. Most fighter radars are frequency agile since they will be operated in close proximity to similar or identical systems. The frequency usually changes in a carefully controlled, completely coherent manner during a CPI.8 This can be a weakness for certain kinds of jamming since the phase and frequency of the next pulse is predictable. Sometimes to counter- act this weakness, the frequency sequence is pseudorandom from a predetermined set with known autocorrelation properties, for example, Frank, Costas, Viterbi, P codes.16 A major difficulty with complex wideband frequency coding is that the phase shift- ers in a phase scanned array must be changed on an intra- or inter-pulse basis greatly complicating beam steering control and absolute T/R channel phase delay. Another challenge is minimizing power supply phase pulling when PRFs and pulsewidths vary over more than 100:1 range. MFAR systems not only have a wide variation in PRF and pulsewidth but also usually exhibit large instant and total bandwidth. Coupled with the large bandwidth is the requirement for long coherent integration times. This requirement naturally leads to extreme stability master oscillators and ultra low-noise synthesizers.44
From an MFAR point of view, the important parameters are volumetric densitieshigh enough to support less than 1/2 wavelength spacing; radiated power densities highenough to support 4 watts per sq. cm.; radiated-to-prime-power efficiencies greaterthan 25%; bandwidth of several GHz on transmit and almost twice that bandwidth onreceive
Отправлено: 30.12.11 23:41. Заголовок: Some modes are used ..
Some modes are used for several operational categories, such as real beam map(RBM), fixed target track (FTT), doppler beam sharpening (DBS), and synthetic aper-ture radar (SAR), used not only for navigation but also for acquisition and weapondelivery to fixed targets.38–43SAR may also be used to detect targets in earthworks ortrenches covered with canvas and a small amount of dirt, which are invisible to EOor IR sensors. Similarly, air-to-surface ranging (A-S Range) and precision velocityupdate (PVU) may be used for weapon support to improve delivery accuracy as wellas navigation.7,9Terrain following and terrain avoidance (TF/TA) is used for navigation at verylow altitudes or in mountainous terrain. Sea surface search (SSS), sea surface track (SST), and inverse synthetic aperture radar (ISAR), which will be described later inthe chapter, are used primarily for the acquisition and recognition of ship targets.Ground moving target indication (GMTI) and ground moving target tracking (GMTT)are used primarily for the acquisition and recognition of surface vehicle targets butalso for recognizing large movements of soldiers and materials in a battle-space. Highpower jamming (HiPwrJam) is a countermeasure available from AESAs due to theirnatural broadband, beam agile, high gain, and high power attributes
AESAs also allowlong range air-to-surface data links (A-S Data Link) through the radar primarily formap imagery. Because there may be thousands of wavelengths and a gain of millionsthrough a radar, automatic gain control and calibration (AGC/CAL) is usually requiredfairly often. Modes optimized for this function are invoked throughout a mission
It is recommended that an A/D be evaluated with large signals at all frequencies within the receiver passband to establish that the quantization noise is as low as theoretically expected and that no spurious signals are produced.
http://dsp-book.narod.ru/skolnik/7913X_15b.pdf Jitter in the sampling time in the A/D converter also limits MTI performance. If pulse compression is done prior to the A/D or if there is no pulse compression, this limit is
TABLE 15.5 Typical Limitation on / Due to A/D Quantization
3.11 ANALOG-TO-DIGITAL CONVERTER Applications. Analog-to-digital converters find numerous applications in modern radar systems. The trend toward digital processing of radar data has resulted in a demand for fast converters that are able to convert data in real time. Digital MTI is an example of a technique requiring such high-speed converters. Here, the synchronous-detector output is sampled at a rate not less than the receiver bandwidth, and the digital result is stored in a large digital memory. Data is read from the memory to allow comparison with corresponding returns from subsequent radar "looks." The flexibility of this method has permitted MTI velocity response characteristics previously unobtainable with analog memory devices. Many tracking radars use a converter to encode the echo in the tracking gate. In this case, a general-purpose computer provides all computations required to track a target and to provide range and velocity outputs. Precise data-smoothing and stabilizing characteristics are provided by the computer. High-speed converters have been used to encode the height information from a stacked-beam radar. This permits an arithmetic interpolation of target position. Errors following conversion are, of course, eliminated. Another application of converters is in the field of digital recording. This is used where vast quantities of data are to be analyzed or where an isolated event is to be analyzed. In this case, the encoded data is stored on magnetic tape. The results are then analyzed in nonreal time with arithmetic accuracy.
Performance Characteristics Signal Bandwidth. The digital data used by the terminal equipment is always sampled. The bandwidth of this "digital signal" is limited to half the sampling frequency. Resolution. The resolution of a converter is determined by the number of bits. For an TV-bit converter, the resolution is Emax/(2^ - 1) if the converter is truly monotonic, that is, if its response to an analog ramp is a uniform progression of binary numbers. This characteristic is usually realized with a slowly changing analog input but must be verified under pulsed conditions. Dynamic Range. If the A/D converter is sampling the two components of the echo vector (/ and Q), each component contains half of the noise power and up to 100 percent of the signal power. The dynamic range is the maximum IF signalto- noise ratio which can be handled by the A/D converter without saturating at any phase condition. Dynamic range (dB) = 67V - 9 - 20 log (o/LSB) (3.28) where N = number of bits including sign cr = rms noise in / or Q LSB = least-significant-bit voltage
numbers introduces an added random error which can be considered as an additional source of noise, requiring an increase in echo strength to achieve the desired detection probability if false-alarm probability is maintained constant. Quantization loss (dB) = 10 log [l + ( M °" - LSB (3-29) L \ CT / J Sampling. When the signal bandwidth is so great that the analog voltage changes significantly from sample to sample, the instantaneous signal may become distorted by the sampling process.15 A slewing error results when the exponential charging is incomplete. An entirely separate lag error results from changes in signal amplitude during the sampling interval. Current flows in the storage capacitor, causing an IR drop, which is still present when the switch is opened. An additional error is introduced by the finite opening time of the switch. The signal tends to be averaged over this interval, and the sampled voltage does not correspond exactly to the voltage at the instant when the switch starts to open. The time required to open the switch is sometimes called the aperture time. Design data specifying the slewing and lag errors is presented in Fig. 3.21. Practical circuits having RC time constants of 3 ns and sampling intervals of 50 ns have been used in high-speed A/D conversion. The resultant slewing error is seen to be less than 0.001 percent, and, at a signal frequency of 0.5 MHz, the lag error is 0.46 percent. It should be emphasized that large sampling errors are not always fatal in a radar system. For example, in an MTI radar the error will repeat from one interpulse period to the next in stationary clutter, and it is therefore removed by subtraction in the canceler.
Отправлено: 31.12.11 23:33. Заголовок: When Oversampling an..
When Oversampling and Averaging Will Work The effectiveness of oversampling and averaging depends on the characteristics of the dominant noise sources. The key requirement is that the noise can be modeled as white noise. Please see Appendix B for a discussion on the characteristics of noise that will benefit from oversampling techniques. Key points to consider are [2] [3]: • The noise must approximate white noise with uniform power spectral density over the frequency band of interest. • The noise amplitude must be sufficient to cause the input signal to change randomly from sample to sample by amounts comparable to at least the distance between two adjacent codes (i.e.,1 LSB - please see Equation 5 in Appendix A). • The input signal can be represented as a random variable that has equal probability of existing at any value between two adjacent ADC codes. Note: Oversampling and averaging techniques will not compensate for ADC integral non-linearity (INL).
Noise that is correlated or cannot be modeled as white noise (such as noise in systems with feedback) will not benefit from oversampling techniques. Additionally,if the quantization noise power is greater than that of natural white noise (e.g.,ther mal noise),then oversampling oversampling and averaging will not be effective. This is often the case in lower resolution ADC’s. The majority of applications using 12- bit ADC’s can benefit from oversampling and averaging.
Performance of subband HFB-based A/D converters Davud Asemani, Jacques Oksman Department of Signal Processing and Electronic Systems Ecole Sup´erieure d’Electricit´e (Supelec) 91192, Gif sur Yvette, France Email: firstname.lastname@supelec.fr
An Oversampled Channelized UWB Receiver Lei Feng, Won Namgoong Department of Electrical Engineering University of Southern California leifeng@usc.edu, namgoong@usc.edu
Two-Dimensional Spatio-Temporal Signal Processing for Dispersion Compensation in Time-Stretched ADC Alireza Tarighat, Member, IEEE, Shalabh Gupta, Student Member, IEEE, Ali H. Sayed, Fellow, IEEE, and Bahram Jalali, Fellow, IEEE
Отправлено: 01.01.12 19:45. Заголовок: July 12, 2011 New U..
July 12, 2011
New U.S Export Regulations Reclassify Linear Technology’s 12-bit 200Msps, 14-bit 125Msps and 16-bit 10Msps ADCs for Export to China & Russia
MILPITAS, CA – July 12, 2011 – Linear Technology Corporation is pleased to announce new Export Classification Control Numbers (ECCN) for their families of high performance, high speed ADCs with sample rates of up to 200Msps at 12-bit, 125Msps at 14-bits and 10Msps at 16-bit resolutions. New U.S. Export Administration Regulations have allowed these devices to be reclassified from ECCN# 3A001 to the less stringent ECCN# 3A991. This new classification provides engineers with the capability to use Linear ADCs to develop and export high performance products that can compete freely on the world market.
Linear Technology offers a wide selection of high performance, low power ADCs that maximize desired system performance. For high performance communications applications, the LTC2207-14 14-bit 105Msps ADC achieves 77.3dB SNR and 98dB SFDR. At 16-bit 10Msps, the LTC2202’s 81.6dB SNR and 100dB SFDR performance is ideal for CCD (charge-coupled device) and infrared cameras, x-ray and cytometry/spectroscopy applications.
For the lowest power, designers in China and Russia can now use 14-bit 25Msps to 125Msps solutions such as the dual LTC2145-14 ADC family with parallel outputs, or LTC2268-14 dual ADCs and LTC2175-14 quad ADCs with serial LVDS outputs, which dissipate approximately 1mW per mega sample per second from a 1.8V supply. These ADCs offer unparalleled performance at ultralow power consumption, maintaining portability in such applications as handheld test and instrumentation, radar/LIDAR, medical imaging, PET/SPECT scanners, military radios, smart antenna systems and a range of low-power communication systems.
In addition to a complete portfolio of high performance ADCs, Linear Technology also offers a wide range of RF mixers, including the LTC5569 and LTC5590/91/92/93 family of dual high dynamic range low power mixers, direct conversion modulators and demodulators, VGAs, filters, power detectors, low-distortion amplifiers and ADC drivers to complete the receive signal chain for next-generation wireless base stations and high performance radios. Linear’s customers can depend on a highly skilled team of applications engineers with a deep knowledge of signal chain design to provide design guidance and technical support to ensure a short design cycle and faster time to market.
The ADC product offering can be found at: www.linear.com/hsadc_nolicense.
About Linear Technology
Linear Technology Corporation, a member of the S&P 500, has been designing, manufacturing and marketing a broad line of high performance analog integrated circuits for major companies worldwide for three decades. The Company's products provide an essential bridge between our analog world and the digital electronics in communications, networking, industrial, automotive, computer, medical, instrumentation, consumer, and military and aerospace systems. Linear Technology produces power management, data conversion, signal conditioning, RF and interface ICs, and µModule® subsystems.
LT, LTC, LTM, µModule, and are registered trademarks of Linear Technology Corp. All other trademarks are the property of their respective owners.
В настоящее время НИИП является головным предприятием по разработке интегрированной радиоэлектронной системы на основе активных фазированных антенных решёток X- и L- диапазонов для истребителя пятого поколения – эта разработка является основным приоритетом института на ближайшие годы.
TI unveils industry's first 12bit 1Gsample/s ADC Steve Bush Wednesday 28 October 2009 14:01 Texas Instruments has unveiled industry's first 12bit 1Gsample/s ADC, the ADS5400. A buffered front-end simplifies external circuit design, and fast sampling means up to four can be used together for 4Gsample/s and 2GHz bandwidth.
"The only devices that come close are also ours, and they sample at 500Msample/s," TI spokesman Heinz-Peter Beckemeyer told Electronics Weekly.
Test and measurement, radar, and signal jamming are the target applications, -------------------------------------------------------------------------------------------
rather than phones or infrastructure.
The monolithic devices, made on the TI's BiCom3 silicon-on-insulator process, are $775 in 100 unit quantities.
Signal to noise ratio (S/N) is 57dB and "almost flat from DC to 2GHz," said Beckemeyer.
Like its 500Msample/s ADS5463 predecessor, architecturally the 5400 is a pipeline converter. ------------------------------------------------------------------------------------------------------------- 12 bit E2V i National folding interpolating
National posle 23 sent .2011 prinadlezit TI ---------------------------------------------------- "You design the individual stages according to what you optimise: signal to noise, or power," said Beckemeyer. "Our challenge was to keep power in the 2.0-2.5W range. The resulting S/N is 10dB better than anything you will find on the market."
Sampling with a single 5400 at 1GHz means DC to 500MHz coverage. Power is around 2.2W. ------------------------------------------------------------------------------------------------------------
Preceded by bandpass filter, the device can also be used to under-sample, covering 500MHz-1GHz, 1.0-1.5GHz, or 1.5-2.0GHz.
Spurious-free dynamic range (SFDR) is, according to Beckemeyer, 77-78dB at DC, 72-73dB at 1GHz, and in the 60dB range at 2GHz.
Sample-and-hold and analogue bandwidth are sufficient to cover DC-2GHz in one go by running four converters in parallel. On-chip hardware allows two or four devices to be interleaved. ------------------------------------------------
"Generally interleaving will generate spurs in the spectrum. ########################################
This converter has gain, phase and amplitude adjustments to remove the spurs," said Beckemeyer.
These adjustments can also be used for balancing ADCs in an I/Q receiver
Other features include user-selectable single or dual-bus LVDS outputs, allowing a choice between I/O speed and pin-count.
Operation is specified from -40 to 85°C, and the package is a 16x16mm thermally-enhanced,100 pin TQFP.
3.Waveform Variations by Mode.Although the specific waveform is hard to pre-
dict, typical waveform variations can be tabulated based on observed behavior of a number of existing A-S radar systems. Table 5.1 shows the range of parameters that can be observed as a function of radar mode. The parameter ranges listed are PRF, pulse width, duty cycle, pulse compression ratio, independent frequency looks, pulses per coherent processing interval (CPI), transmitted bandwidth, and total pulses in a Time-On-Target (TOT).
Obviously, most radars do not contain all of this variation, but modes exist in many fighter aircraft, which represent a good fraction of the parameter range. Most fighter radars are frequency agile since they will be operated in close proximity to similar or identical systems. The frequency usually changes in a carefully controlled, completely coherent manner during a CPI.8 This can be a weakness for certain kinds of jamming since the phase and frequency of the next pulse is predictable. Sometimes to counter- act this weakness, the frequency sequence is pseudorandom from a predetermined set with known autocorrelation properties, for example, Frank, Costas, Viterbi, P codes.16 A major difficulty with complex wideband frequency coding is that the phase shift- ers in a phase scanned array must be changed on an intra- or inter-pulse basis greatly complicating beam steering control and absolute T/R channel phase delay. Another challenge is minimizing power supply phase pulling when PRFs and pulsewidths vary over more than 100:1 range. MFAR systems not only have a wide variation in PRF and pulsewidth but also usually exhibit large instant and total bandwidth. Coupled with the large bandwidth is the requirement for long coherent integration times. This requirement naturally leads to extreme stability master oscillators and ultra low-noise synthesizers.44
From an MFAR point of view, the important parameters are volumetric densitieshigh enough to support less than 1/2 wavelength spacing; radiated power densities highenough to support 4 watts per sq. cm.; radiated-to-prime-power efficiencies greaterthan 25%; bandwidth of several GHz on transmit and almost twice that bandwidth onreceive
For operation at Nyquist (Fin~Fs/2) and above, the clock phase noise (also called jitter) has direct impact on SNR. Jitter can be split in 2 components: external jitter (due to the sources used, or potential board routing issues), and internal jitter (generated in the ADC by thermal noise on clock path, coupling with other signals, or poor power supply rejection). Therefore internal jitter is also a very important parameter of the ADC. Parameters to consider for a high speed ADC are therefore: THD, SFDR, IMD (multitone), SNR, Noise Power Ratio (for broadband application), ADC added Jitter (for 2nd Nyquist application).
3.2 Quantifier Quantifier structure choice is a key issue in the design of an ADC, specially when we are looking simultaneously for speed, accuracy and power efficiency. Pipeline and sub-ranging architectures are discarded, because for this sampling range they are not relevant, especially regarding B.E.R (Bit Error Rate) issue. -------------------------------------------------- No TI 1 gsps ,12 bit ADS5400 - 3 state pipeline 14 bit ,400 msps ADS5474 -pipeline
A full flash architecture is also not acceptable because of loading effect caused at T/H output due to too many comparators (210+1), and also because of power spillage that this architecture would imply. Finally we retained a successively folded and interpolated architecture which offers the best trade-off between speed, accuracy and power dissipation. The MSBs are generated by a coarse cycle pointer, and are corrected in accordance with LSB’s transition in the logic part. Gain adjustment is made by controlling the bias of the reference resistor chain.
D. ADC Characterization Results 1) ADC Single Tone FFT Computation at 3 GS/s in 1st, 2nd and 3rd Nyquist zones At 3 GS/s in the 1st Nyquist (Fin=1495MHz, -1dBFS), an ENOB of 8.1 Bit and an SFDR of 59 dBc is achieved (Fig. 3). In the 2nd Nyquist (Fin=2995MHz, -3 dBFS), an ENOB of 8.0 Bit is still achieved, with an SFDR performance of 58 dBc (Fig. 4). With Fin=3995MHz (-3 dBFS), corresponding to the S_Band upper limit, the ENOB is still 7.7 Bit, with an SFDR of 55 dBc, and the SNR is 49.5 dBFS. The SNR roll off versus input frequency is related to the voltage noise induced by the 120 fs rms internal sampling clock jitter of the ADC. The large linearity roll off over frequency is related to the large signal dynamics of the front-end Track and Hold, which improves for smaller signals. The 0dBFS ADC Full Scale reference voltage span is 500 mV, and Full Scale input power is -2dBm if single-ended driven in 50 Щ and -5 dBm if differentially driven in 100 Щ termination. At 3 GS/s and Fin = 3 GHz, an SNR of 51 dB is achieved, leading to an FFT noise floor of: SNR + 10log(N/2) = 51dB+10log(16384)=93dB per 32K FFT bin width. The normalized noise floor in dBc/Hz at Fs=3 GS/s is 51 dB + 10log(Fs/2)=142.7dBc/Hz. Since ADC Full Scale differential input power is -5dBm, the normalized (per/Herz) Noise floor is -5dBm-143dB = -148 dBm/Herz. The ADC total noise power includes the input referred thermal noise and the voltage noise induced by time jitter. Therefore the contribution of the ADC to overall system noise figure can be calculated.
Отправлено: 03.01.12 23:46. Заголовок: Software Defined Mul..
Software Defined Multi-Channel Radar Receivers for X-band Radars Missile Defense Agency - STTR FY2009B - Topic MDA09-T003 Opens: August 24, 2009 - Closes: September 23, 2009 --------------------------------------------------------------------------------
MDA09-T003 TITLE: Software Defined Multi-Channel Radar Receivers for X-band Radars
TECHNOLOGY AREAS: Sensors, Electronics
The technology within this topic is restricted under the International Traffic in Arms Regulation (ITAR), which controls the export and import of defense-related material and services. Offerors must disclose any proposed use of foreign nationals, their country of origin, and what tasks each would accomplish in the statement of work in accordance with section 3.5.b.(7) of the solicitation.
OBJECTIVE: Investigate and develop Software-Defined Multi-channel Receivers to enhance X-Band radar systems performance.
DESCRIPTION: Future X-Band radar systems will employ low-cost antenna array technology and digital beamforming architecture that requires multiple receiver channels. Demonstrating the utility of software defined, scalable multi-channel receiver technology that reduces cost, weight, and size while enhancing radar system flexibility and performance is the optimal goal of this research. With recent development of the state-of-the-art receiver technology coupled with high-speed computing devices, multi-channel receiver (consisting of up to 100s of channels) controlled by software may possible. The advantage of software defined multi-channel receiver is that the reconfiguration of hardware components can be done relatively quickly. The benefit of employing software defined receiver is that the implementation would rely heavily on the digital signal processing algorithm and requiring fewer hardware components. Subsequent benefits such as improvement in dynamic range, quadrature coherency, reliability, and low cost. The primary objective of this research is to investigate the feasibility of software-defined technology that offers the potential of a low-cost robust multi-channel receiver solution. The multi-channel receive takes X-Band RF signals and outputs digitized In-phase and Quadrature (I&Q) data. The receiver should cover a 25-40% operating bandwidth centered at X-Band. The receiver should cover a tunable instantaneous bandwidth of 1GHz (goal), 400MHz (threshold), with an instantaneous dynamic range of 52+ dB. The control interfaces should utilize Open System Architecture to the maximum extend possible for ease of integration within the radar systems.
PHASE I: Investigate the feasibility, technical issues, and risks of developing software-defined multi-channel receiver at X-Band. Conduct computer modeling and demonstrate proof of concept implementation. The research will result in a detail report on how the software defined multi-channel receiver would be built to meet the performance while attaining the low cost and small size objective.
PHASE II: Demonstrate the operation of the developed prototype software defined multi-channel receiver using low-cost components. Validate performance, cost and reliability benefits to be achieved through a prototype device. Quatify the benefits of digital signal processing implemention and approach and identify commercial radar application opportunity.
PHASE III: Design and validate the software defined multi-channel receiver prototype developed in Phase II for X-Band radar systems for military and commercial applications. Work closely with missile defense agency (MDA) to target potential technology insertion and integration into MDA ballistic missile defense systems.
COMMERCIALIZATION: The proposed technology has a number of related commercial applications in radio frequency (RF) sensors. Commercial radar systems, commercial RF communications systems that require software defined multi-channel receiver.
REFERENCES: 1. J. H. Reed, "Software Radio A Modern Approach to Radio Engineering", Prentice Hall Communications Engineering and Emerging Technologies Series, 2002.
2. R. Seal, J. Urbina, M. Sulzer, S. Gonzalez, N. Aponte, "Design of an FPGA-based radar controller", National Radio Science Meeting, Boulder, CO, Jan 2008.
3. J. Mitola, "Cognitive radio: an integrated agent architecture for software defined radio", Ph.D. dissertation, KTH Royal Institute of Technology, Stockholm, Sweden, 2000.
4. T. Quach et al, "X-Band Receiver Front-End Chip in Silicon Germanium Technology", IEEE 8th Topical Meeting on Silicon for RF Systems, Jan 2008.
5. R. Dragenmeister et al, "Multi-Chip-Module Based X-Band Receiver Utilizing Silicon Germanium MMICs", GOMACTECH 2008, Mar. 2008.
KEYWORDS: Antenna Array, Multi-channel Receiver, Analog to digital converter, Radar receiver, Digital Beamforming, phased array radar.
TPOC: Dr. Seng Hong Phone: 937.255.3802 X3449 Fax: 703.882.6350 Email: seng.hong@wpafb.af.mil
Отправлено: 04.01.12 00:25. Заголовок: For example, look at..
For example, look at US PCS of 5 MHz. If the lowest frequency were translated to 1 MHz, the highest frequency of the band would be at 6 MHz. However, if a carrier were operational at the bottom of the band (1 MHz IF frequency), the second and third harmonic would fall at 2 and 3 MHz respectively, right in the middle of the band. These harmonics definitely can disrupt calls in a wide dynamic such as GSM or AMPS. Now consider the case where the bottom frequency of the band was translated to 5.1 MHz instead of 1 MHz. The upper frequency would align with 10.1 MHz. Now a quick look at the harmonics shows that the second harmonic of 5.1 MHz would fall at 10.2 MHz, outside the band of interest. The higher the IF frequency, the more spread out the harmonics and signals of interest become. In a practical sense, the IF frequency should be as high as the ADC could reasonably process.
W 35 ghz MMW radar Lincoln laboratory s 13.7 metr aantennoj i polosoj signala 1000 mhz(potom 2000 mhz)
w nachale 90 posle mnogokratnix preobre. chastoti ispolzowalsja strech processing
s 10 bit 20 msps AZP w üpolose 2.5 mhz-7.5 mhz
Sowetskie AZP imeli te ze dannie ( pri nizkom wixode godnix)
koipja s linka
Уважаемый, Carbon, хотел бы внести небольшое уточнение. Приведенный Вами на фото АЦП 1107ПВ3Б из "Венты" имел частоту преобразования 50МГц, а вот 1107ПВ3А имел уже 100МГц. С такой же частотой 100МГц 1107ПВ4 (Тема "Веда") имел разрядность 8. И уже на излете советской власти (как писал уважаемый Georg)появился лучший советский АЦП 1107ПВ6 - 10р 15 МГц.
В ГУП НПЦ «Элвис» разработаны отечественные микросхемы двухканального аналого-цифрового контроллера ввода сигналов 9008ВГ1Я. Приборы могут быть использованы в качестве обычного двухканального АЦП, а также для замены AD9225, AD9240, ADS850 (Analog Devices), LTC2246, LTC2226 (Linear Technology). Микросхемы выполнены в виде многокристального модуля и содержат два кристалла 14-разрядных АЦП конвейерного типа с частотой оцифровки до 20 МГц и цифровой контроллер. Кристаллы изготовлены по 0,25 мкм технологии и размещены в 192-выводном корпусе BGA размером 17х17 мм. Диапазон рабочих температур от -60 до 85°C.
9008ВГ1Я оцифровывает внешние сигналы/изображения, хранит их в буферной памяти типа FIFO и выводит информационный поток через интерфейс подключения к порту памяти (MPORT) процессоров серии «Мультикор», а также совместимых по интерфейсу ИС для дальнейшей обработки процессором.
Кроме того, цифровой контроллер позволяет выводить данные непосредственно с выходов АЦП (минуя буферную память и интерфейс MPORT), например, в 1288ХК1Т (Digital Down Converter).
Практическое применение микросхем возможно в таких областях как системы ввода изображения, в том числе системы тепловидения; радиосвязь; радиолокация; гидроакустические системы; измерительная техника; системы сбора данных; системы управления; системы промышленного контроля; и в других устройствах, позволяющих принимать и обрабатывать отсчеты АЦП в реальном времени.
Макетные образцы микросхем 9008ВГ1Я имеют маркировку 1892ВГ1Я или 2008ВГ1Я.
Основные характеристики
тактовая частота АЦП 20 МГц; частота входного сигнала до 140 МГц; буферная память типа FIFO глубиной 4096х2 отсчетов; возможность непосредственного доступа к встроенным АЦП; интерфейс памяти, позволяющий имитировать режимы работы SRAM, SDRAM; 32/16-разрядный режимы работы интерфейса памяти MPORT с частотой до 100 МГц; возможность объединения микросхем в группы для совместной работы на одной выходной шине данных - до 8 микросхем в составе двух групп; пиковое потребление 800 мВт; питание: цифровое: 2.5 В ядро, 3.3В периферия; аналоговое: 3.3 В; допустимое изменение напряжения ±5%; диапазон рабочих температур от -60 до 85°C; корпус BGA-192, 17х17 мм, шаг 1 мм. Для заказа микросхем и по всем интересующим вопросам обращайтесь по телефону: (499) 729-7110 begin_of_the_skype_highlighting (499) 729-7110 end_of_the_skype_highlighting, доб.114; факс: (495) 913-3188. E-mail: market@elvees.com.
Источник: Элвис
Neobxodimo priwlech ser'eznie organizacionnie i finasowie resursi i po programme zameschenija
dowesti 2*!4 bit *20 msps do 2*14 bit *200-300 msps
Быстродействующие 14-разрядные ЦАП с токовым выходом серии 1273 В статье описаны микросхемы быстродействующих широкополосных 14-разрядных ЦАП серии 1273 разработки ФГУП НИИЭТ, г. Воронеж. Эти ЦАП являются представителями семейства TxDAC и оптимизированы для использования в передающих трактах систем широкополосной связи, оборудовании связи, беспроводных локальных сетях, инструментальных системах, а также в контрольно-измерительной аппаратуре и устройствах прямого цифрового синтеза (DDS). Прототипами микросхем являются изделия фирмы Analog Devices.
М
икросхемы ЦАП и АЦП относятся к числу компонентов, наиболее широко распространенных на мировом рынке электроники, поскольку они объединяют цифровые и аналоговые блоки различных систем РЭА. Среди приборов этого класса важное место занимают быстродействующие ЦАП с разрядностью 8—16 бит, ориентированные, прежде всего, на беспроводные средства связи и инструментальные системы. Для реализации современного уровня требований к таким ЦАП необходимо решать задачи улучшения их динамических характеристик, а также повышения разрешения и скорости восстановления выходного сигнала.
В работе [1] отмечается, что быстродействующие ЦАП для средств связи в большинстве своем выполняются с использованием сегментированной архитектуры на источниках тока (segmented current source architecture), обеспечивающей высокую точность установления сигнала. При этом помимо стандартных параметров, определяющих свойства быстродействующих ЦАП, например производительность, частота обновления выходных данных, время установления, интегральная (INL) и дифференциальная (DNL) нелинейность, вводятся и такие специальные параметры как SFDR — динамический диапазон, свободный от паразитных составляющих (гармоник), IMD — коэффициент интермодуляционных искажений, SNR — отношение сигнал/шум на частоте несущей и др.
Разработка первого отечественного быстродействующего 14-разрядного ЦАП с сегментированной архитектурой на источниках тока 1273ПА4Т была выполнена ФГУП НИИЭТ в 2006 г. Производительность ЦАП составляет до 125 млн выб./с (MSPS). Прототипом микросхемы является AD9764 фирмы Analog Devices. В настоящее время проводится разработка еще трех типов ЦАП с подобной архитектурой — 1273ПА5У, 1273ПА6У и 1273ПА7Т. Микросхемы обеспечивают высокую производительность и имеют в составе различные дополнительные устройства, которые значительно расширяют их функциональные возможности. Сравнительные параметры всех четырех типов ЦАП приведены в таблице 1.
Автор: Валерий Скляр, зам. нач. отд., ФГУП НИИЭТ; Владимир Горохов, зам. гл. инженера, ФГУП НИИЭТ; Юрий Борисов, вед. инженер-конструктор, ФГУП НИИЭТ; Денис Горбунов, инженер-конструктор 1-й кат., ФГУП НИИЭТ; Сергей Битюцких, инженер-конструктор 1-й кат., ФГУП НИИЭТ
pushed the core technology to 14-bits with the release of the AD6644 14-bit 65-MSPS ADC in 1999, the AD6645 14-bit 80-MSPS ADC in 2001, and a 105-MSPS version of the AD6645 in 2003. Although these ADCs use the error-corrected pipelined subranging architecture, the internal building block core ADCs utilize the MagAMP™ architecture. Page
The ISLA216P is a family of low power, high performance 16-bit analog-to-digital converters. Designed with Intersil’s proprietary FemtoCharge™ technology on a standard CMOS process, the family supports sampling rates of up to 250MSPS.
• Total Power Consumption = 786mW @ 250MSPS
Digital output data is presented in selectable LVDS or CMOS formats.
Applications • Radar Array Processing
SNR 72.1 db/363 mhz 71.1db/461 mhz 69.2db/605 mhz SINAD 71.6 69.2 65.7 ENOB 11.60 11.20 10.62 SFDR 81 db 73 db 67 db
Functional Description The ISLA216P25 is based upon a 16-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 18). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit of charge. Proprietary charge-domain techniques are used to successively compare the input to a series of reference charges. Decisions made during the successive approximation operations determine the digital code for each input value. Digital error correction is also applied, resulting in a total latency of 10 clock cycles. This is evident to the user as a latency between the start of a conversion and the data being available on the digital outputs.
dlja srawnenija AD9467 ,wische 300 mhz parametri ne normirowanni -----------------------------------------------------------------------------------
pervij pok 2 volta ,wtoroj dlja 2.5 volta p-p analog input
SNR 73.3/74.6 db /300 mhz SINAD 73.1 dbfs/ 74.4 ENOB 11.9/12.1 db SFDR 93/90 dBFS
THEORY OF OPERATION The AD9467 architecture consists of an input-buffered pipe-lined ADC that consists of a 3-bit first stage, a 4-bit second stage, followed by four 3-bit stages and a final 3-bit flash. Each stage provides sufficient overlap to correct for flash errors in the preceding stage. The input buffer provides a linear high input impedance (for ease of drive) and reduces the kick-back from the ADC. The buffer is optimized for high linearity, low noise, and low power. The quantized outputs from each stage are combined into a final 16-bit result in the digital correction logic. The pipelined architecture permits the first stage to operate with a new input sample while the remaining stages operate with preceding samples. Sampling occurs on the rising edge of the clock. Each stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched-capacitor DAC and an interstage residue amplifier (for example, a multiplying digital-to-analog converter (MDAC)). The residue amplifier magnifies the difference between the reconstructed DAC output and the flash input for the next stage in the pipeline. One bit of redundancy is used in each stage to facilitate digital correction of flash errors. The last stage simply consists of a flash ADC. The output staging block aligns the data, corrects errors, and passes the data to the output buffers.
Bandwidths that are 10% of the radar’s carrier frequency are reasonably straightforward to implement (e.g., 500 MHz at C-band or 1000 MHz at X-band).
Processing 500-MHz-bandwidth signals in some conventional pulse-compression scheme was not feasible with the technology available at the time of ALCOR’s inception. Consequently, it was necessary to greatly reduce signal bandwidth while preserving range resolution. This is accomplished in a timebandwidth exchange technique (originated at the Airborne Instrument Laboratory, in Mineola, New York) called stretch processing [4], which retains range resolution but restricts range coverage to a narrow thirtymeter window. In order to acquire and track targets and designate desired targets to the thirty-meter wideband window, ALCOR has a narrowband waveform with a duration of 10.2 мsec and bandwidth of 6 MHz. This narrowband waveform has a much larger 2.5-km range data window.
During 1972 and 1973, Lincoln Laboratory devel-oped a 512-MHz-bandwidth (on a 1-GHz interme-diate frequency [IF])
ALCOR operates at C-band (5672 MHz) with a signal bandwidth of 512 MHz that yields a range resolution of 0.5 m. (The ALCOR signal was heavily weighted to produce low range sidelobes with the concurrent broadening of the resolution.) Its widebandwidth waveform is a 10-мsec pulse linearly swept over the 512-MHz frequency range. High signal-tonoise ratio of 23 dB per pulse on a one-square-meter target at a range of a thousand kilometers is achieved
1.28.09.1999 Maxim 8bit/1.5gsps/FLASH MAX108 2. 10/15/2003 Atmel/e2V 10bit/2gsps/FOLDING-INTERPOLATIG TS83102G0B 3.October 2009 TI 12 bit/1gsps/3 stage PIPELINE ADS5400 4. May 24, 2010 National Semiconductor/TI 2*12 bit *1.8 gsps ADC12D1800 FOLDING INTERPOLATING 5. xx.xx.201? XXX company introduce industry first single core 14 bit 1 gsps ADC architectur -XXX ?
SNR = 70 dbc by Fin 700 ? 1000 mhz ?
1.28.09.1999 Maxim 8bit/1.5gsps/FLASH -------------------- September 28, 1999-Maxim Integrated Products introduces the MAX108 The MAX108 is the first 8-bit, 1.5Gsps monolithic ADC to achieve a typical 47dB SINAD and 54dB SFDR at 1.5GHz http://www.maxim-ic.com/company/newsroom/pr_products/show.mvp/npk/38 The MAX108 achieves a full 47dB SINAD and 54dB SFDR at 750MHz (Nyquist) input frequency. The MAX108 achieves this high performance through both innovative design and the use of Maxim's proprietary 27GHz GST-2 IC bipolar process. An integrated, fully differential input track/hold (T/H) combined with precision laser-trimmed resistors produce a typical INL and DNL of less than ±0.25LSB, a full-power bandwidth of 2.2GHz, and less than 0.5ps aperture jitter.
10/15/2003 - Atmel® Corporation (Nasdaq: ATML) The TS83102G0B is the first ADC available that combines 10-bit resolution, 2 Gsps maximum The TS83102G0B delivers excellent performance while only dissipating 4.6W. SFDR (spurious free dynamic range) is 60dBFS at 1.4Gsps/700MHz input frequency, and still in the 55dBFS range at 2Gsps / 2GHz input frequency. Two-tone third order intermodulation distortion is 65dB at 1.4Gsps over a 500MHz band centered around 1GHz, allowing to digitise high IF broadband signals with adjacent channels with a very low level of parasitic spectrum components. It is further complemented by added features such as data ready output, asynchronous data ready reset and gain controls.
TI unveils industry's first 12bit 1Gsample/s ADC Steve Bush Wednesday 28 October 2009 14:01 Texas Instruments has unveiled industry's first 12bit 1Gsample/s ADC, the ADS5400. A buffered front-end simplifies external circuit design, and fast sampling means up to four can be used together for 4Gsample/s and 2GHz bandwidth.
Preceded by bandpass filter, the device can also be used to under-sample, covering 500MHz-1GHz, 1.0-1.5GHz, or 1.5-2.0GHz.
Spurious-free dynamic range (SFDR) is, according to Beckemeyer, 77-78dB at DC, 72-73dB at 1GHz, and in the 60dB range at 2GHz.
Sample-and-hold and analogue bandwidth are sufficient to cover DC-2GHz in one go by running four converters in parallel. On-chip hardware allows two or four devices to be interleaved.
SANTA CLARA, Calif., May 24 /PRNewswire-FirstCall/ — National Semiconductor Corp. (NYSE: NSM) today introduced the Industry’s fastest 12-bit analog-to-digital converter (ADC). At 3.6 Giga-samples per second (GSPS), the ADC12D1800 is 3.6 times faster than any other available 12-bit device. The ADC’s dynamic performance of -147 dBm/Hz noise floor, 52 dB noise power ratio (NPR) and -61 dBFS intermodulation distortion (IMD) enables a new generation of software-defined radio (SDR) architectures and applications.
5. xx.xx.201? XXX company introduce industry first single core 14 bit 1 gsps ADC
The practical signal bandwidth is close to 1GHz and the range resolution is close to 15cm.
The core of the TRITON VXS-1 is a Xilinx Virtex-II Pro FPGA circuit along with a 10bit ADC and a 12bit DAC. Both converters can operate at 2 GSamples/sec, giving a Nyquist digital signal bandwidth of 1 GHz. The analog 3 dB-bandwidth extends from 3 MHz to 3 GHz.
By interleaving Intersil's low power, high sample rate ADCs, it is possible to achieve a combination of ultra-high sample rate and very high dynamic range that is not available in today’s stand-alone ADCs.
This reference design demonstrates the performance attainable by combining Intersil's ADC technology and SP Devices interleaving algorithms. In this design, 4 ISLA112P50 12-bit, 500 MSPS analog-to-digital converters are interleaved to sample at a rate of 2.0 GSPS. At this sampling rate, the reference design provides over 6dB more SNR and 13dB better SFDR than the best alternative stand-alone ADC.
Collaboration of Intersil and SP Devices Demonstrates 4-way Interleaving of Intersil 500MSPS ISLA112P50s Sample Rate: 2.0 GSPS Resolution: 12 Bits Interleave Correction Details SP Devices’s ADX4 provides real-time, digital, FPGA based digital interleave correction of four ISLA112P50s Performance SNR = 65.5 dBfs @ Fin = 190MHz, a 6dB improvement over current best standalone 2GSPS ADCs SFDR = 82 dBc @ Fin = 190MHz, a 13dB SFDR improvement over current best standalone 2GSPS ADCS
SP Devices' time-interleaving technology in module from Texas Instruments TI introduces 14-bit, 800-MSPS digitizer solution leveraging industry's fastest data converters
DALLAS -- Sept. 4, 2008 -- Texas Instruments Incorporated (TI) (NYSE: TXN) today introduced an evaluation module (EVM) that combines TI's fastest 14-bit analog-to-digital converters (ADCs) in an interleaved fashion with a Xilinx® Virtex®-5 FPGA to create the best-performing high-speed digitizer solution in the market. The FPGA comes pre-installed with SP Devices' proprietary time-interleaving technology to eliminate interleaving spurs, which enhances performance and facilitates rapid system-level evaluation for wireless communications, military, test and measurement applications. The EVM joins TI's portfolio of support tools for customers using high-speed data converters in wide-bandwidth applications. (See www.ti.com/ads5474adx-evm-pr.)
The ADS5474ADX-EVM incorporates two of TI's ADS5474 ADCs, a Xilinx Virtex-5 FPGA and SP Devices' proprietary time-interleaving technology to deliver an 800-MSPS ADC solution. The SP Devices' software continuously monitors the system and removes ADC gain, clocking and temperature mismatches to reduce the interleaving spurs below the ADC harmonic spurs. By reducing the interleaving spurs, the software increases spurious free dynamic range (SFDR) from 45.78 dBc to 86.44 dBc for a 70-MHz input signal. ##################################################
Na dannoj Fin y 16 bit 250 msps ADC Intersil 216p25 ili Analog Device AD9467
SFDR 93-95 dbc
"Addressing the industry's ever-increasing demand for higher sampling speeds and extended bandwidth is important to us," said Jonas Nilsson, CEO of SP Devices. "Combining SP Devices' innovative interleaving technology with TI's market-leading data converters allows us to extend performance boundaries of high-speed ADCs, which will enable exciting new applications including multi-carrier systems, software-defined radio, advanced imaging and beyond."
In addition to improved performance for these complex systems, the EVM simplifies evaluation and helps designers bring end systems to market faster. For instance, the continuous monitoring of the ADC's mismatch eliminates the need for an off-line re-calibration routine to account for changes in temperature or other environmental factors, significantly reducing system evaluation and design time.
"With this latest EVM, customers can focus on prototyping advanced architectures to optimize system-level performance in these complex applications, rather than concentrating on developing an interleaving solution," said Mark Stropoli, worldwide marketing manager for TI's High Speed Products.
Availability and packaging
The ADS5474ADX-EVM is available today from TI at www.ti.com/ads5474. Pricing for the EVM is $1,999. The ADS5474ADX-EVM is the latest addition to TI's world-class high-speed and precision data converter tools designed to address a range of applications. For more information, visit the Analog eLabTM Design Center at www.ti.com/analogelab.
Further information about SP Devices' interleaving technology is available at www.spdevices.com.
The high sampling rate of the LTC2208 provides an advantage when used in oversampling applications, using processing gain to improve the receiver’s SNR performance. Capturing a signal bandwidth of 30MHz requires an ADC with a sample rate of at least 60Msps. However if the signal was sampled at a higher rate of 120Msps the broadband noise fl oor is reduced by 3dB as given by the following equation
Отправлено: 08.01.12 22:10. Заголовок: It achieves a small-..
It achieves a small-signal SNR of 72 dBFS and a SFDR greater than 90 dBFS with a 169 MHz input frequency. Large signal performance yields a SNR of 68.3 dBFS and SFDR of 77 dBFS at 169 MHz. In
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