Отправлено: 13.11.09 15:19. Заголовок: Operazionnie ysiliteli ,ZAP/AZP & (продолжение)

1941: First (vacuum tube) op-amp

An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V.
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It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs.
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This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that
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would not have been possible otherwise.[3]
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http://en.wikipedia.org/wiki/Operational_amplifier

 Отправлено: 17.10.10 14:36. Заголовок: http://datasheets.ma..

 Отправлено: 17.10.10 15:02. Заголовок: lutschij 16-bit 1..

lutschij 16-bit 170'/ 200 msps y Texas Instruments ADS5484 -170 ,ADS5485 -200 msps

http://focus.ti.com/lit/ds/symlink/ads5485.pdf<\/u><\/a>

SNR -75 db na 170 mgz
SFDR -78 db na 170 mgz
HD2 -78 db na 170 mgz

ENOB Effective number of bits wsego na 10 mgz ot 16 ostaetsja 12.1 bit
----------------------------------------------------------------------------------

 Отправлено: 17.10.10 15:12. Заголовок: http://cds.linear.co..

 Отправлено: 17.10.10 15:21. Заголовок: lutschij 16 bit 16..

lutschij 16 bit 160 msps ot Linear technology LTC2209

http://cds.linear.com/docs/Datasheet/2209fa.pdf<\/u><\/a>

Signal Noise 250 mgz -73.5 db
SFDR -75 db/84db (ot wxoda) dlja HD2/HD3

 Отправлено: 17.10.10 15:37. Заголовок: lutschij 14 -bit ot ..

lutschij 14 -bit ot TI 400 msps ADS5474

http://focus.ti.com/lit/ds/symlink/ads5474.pdf<\/u><\/a>

SNR 451 mgz - 68.4 db
999 mgz -64.7 db
SFDR 451 mgz -71 db
999 mgz -46 db

yzen na 230 mgz ENOB 10.9 bit ot 14 ,wische esche xuze ...

 Отправлено: 17.10.10 15:49. Заголовок: lutschij 12 bit on ..

lutschij 12 bit on National ,wozmozno lutschij skorostnoj 12 bit ADC sredi serijnoj produkzii

http://www.national.com/ds/DC/ADC12D1800.pdf<\/u><\/a>

The 12-bit, 3.6 GSPS ADC12D1800

ENOB 8.4 bita na 1448 mgz typ
8.5 bita na 1147 mgz
SINAD 52.5 db na 1448 mgz
52.9 db na 1147 mgz
SNR 53.1 db na 1448 mgz
53.9 db na 1147 mgz
SFDR 60.3 db na 1448 mgz
60.2 db na 1147 mgz
Power 4.4W (typ)

2.0 Applications
■ Wideband Communications
■ Data Acquisition Systems
■ RADAR/LIDAR
■ Set-top Box
■ Consumer RF
■ Software Defined Radio

The product is packaged in a leaded or lead-free 292-ball
thermally enhanced BGA package over the rated industrial
temperature range of -40°C to +85°C

 Отправлено: 17.10.10 16:03. Заголовок: lutschij 12 bit ot ..

lutschij 12 bit ot Texas instruments ADS5400

http://focus.ti.com/lit/ds/symlink/ads5400.pdf<\/u><\/a>
12-Bit, 1-GSPS Analog-to-Digital Converter
Check for Samples: ADS5400

APPLICATIONS

• Test and Measurement Instrumentation
• Ultra-Wide Band Software-Defined Radio
• Signal Intelligence and Jamming
• Radar

Total Power Dissipation: 2.15 W
ADS5400 is built on Texas Instrument's complementary bipolar process (BiCom3)
The ADS5400 is available in a TQFP-100 PowerPAD™ package

SNR 1200 mgz -57.6 db
1700 mgz - 55.7 db

SFDR 1200 mgz - 66 db
1700 mgz -56 db

SINAD 1200 mgz -57.5 db
1700 mgz -54.2 db

ENOB 850 mgz -9.3 db typ 8.67 minimum
----------------------------------

Price is $775 each/100. TEXAS INSTRUMENTS INC., Dallas, TX.
##########################################


srawni s dannimi wische s ychetowm togo chto National sdwoennij 2 *1.8 gsps

 Отправлено: 17.10.10 16:22. Заголовок: smotri wische dannie..

smotri wische dannie MAX109

http://www.maxim-ic.com/app-notes/index.mvp/id/810<\/u><\/a>


APPLICATION NOTE 810 Sep 16, 2010
Understanding flash ADCs

Abstract: Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal
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to a digital signal. Flash ADCs are ideal for applications requiring very large bandwidth, but they consume more power than other ADC architectures and are generally limited to 8-bit resolution. This tutorial will discuss flash converters and compare them with other converter types.

Introduction
Flash analog-to-digital converters, also known as parallel ADCs, are the fastest way to convert an analog signal to a digital signal. Flash ADCs are suitable for applications requiring very large bandwidths. However, these converters consume considerable power, have relatively low resolution, and can be quite expensive. This limits them to high-frequency applications that typically cannot be addressed any other way. Typical examples include data acquisition, satellite communication, radar processing, sampling oscilloscopes, and high-density disk drives.

This tutorial will discuss flash converters and compare them with other converter types.

Architectural details
Flash ADCs are made by cascading high-speed comparators. Figure 1 shows a typical flash ADC block diagram. For an N-bit converter, the circuit employs 2N-1 comparators. A resistive-divider with 2N resistors provides the reference voltage. The reference voltage for each comparator is one least significant bit (LSB) greater than the reference voltage for the comparator immediately below it. Each comparator produces a 1 when its analog input voltage is higher than the reference voltage applied to it. Otherwise, the comparator output is 0. Thus, if the analog input is between VX4 and VX5, comparators X1 through X4 produce 1s and the remaining comparators produce 0s. The point where the code changes from ones to zeros is the point at which the input signal becomes smaller than the respective comparator reference-voltage levels.


Figure 1. Flash ADC architecture. If the analog input is between VX4 and VX5, comparators X1 through X4 produce 1s and the remaining comparators produce 0s.

This architecture is known as thermometer code encoding. This name is used because the design is similar to a mercury thermometer, in which the mercury column always rises to the appropriate temperature and no mercury is present above that temperature. The thermometer code is then decoded to the appropriate digital output code.

The comparators are typically a cascade of wideband low-gain stages. They are low gain because at high frequencies it is difficult to obtain both wide bandwidth and high gain. The comparators are designed for low-voltage offset, so that the input offset of each comparator is smaller than an LSB of the ADC. Otherwise, the comparator's offset could falsely trip the comparator, resulting in a digital output code that is not representative of a thermometer code. A regenerative latch at each comparator output stores the result. The latch has positive feedback, so that the end state is forced to either a 1 or a 0.

Given these basics, some adjustments are needed to optimize the flash converter architecture.

Sparkle codes
Normally, the comparator outputs will be a thermometer code, such as 00011111. Errors can cause an output like 00010111, meaning that there is a spurious zero in the result. This out-of-sequence 0 is called a sparkle, which is caused by imperfect input settling or comparator timing mismatch. The magnitude of the error can be quite large. Modern converters like the MAX109/MAX104 employ an input track-and-hold in front of the ADC along with an encoding technique that suppresses sparkle codes.

Metastability
When the digital output from a comparator is ambiguous (neither a 1 nor a 0), the output is defined as metastable. Metastability can be reduced by allowing more time for regeneration. Gray-code encoding, which allows only 1 bit in the output to change at a time, can greatly improve metastability. . Thus, the comparator outputs are first converted to gray-code encoding and then later decoded to binary, if desired.

Another problem occurs when a metastable output drives two distinct circuits. It is possible for one circuit to declare the input a 1, while the other circuit thinks that it is a 0. This can create major errors. To avoid this conflict, only one circuit should sense a potentially mestatable output.

Input signal-frequency dependence
When the input signal changes before all the comparators have completed their tasks, the ADC's performance is adversely impacted. The most serious impact is a drop-off in signal-to-noise ratio (SNR) plus distortion (SINAD) as the frequency of the analog input frequency increases.

Measuring spurious-free dynamic range (SFDR) is another good way to observe converter performance. The "effective bits" achieved by the ADC is a function of input frequency; it can be improved by adding a track-and-hold (T/H) circuit in front of the ADC. The T/H circuit allows dramatic improvement, especially when input frequencies approach the Nyquist frequency, as shown in Figure 2 (taken from the MAX104 data sheet). Parts without T/H show a significant drop-off in SFDR.


Figure 2. Spurious-free dynamic range as a function of input frequency.

Clock jitter
SNR is degraded when there is jitter in the sampling clock. This becomes noticeable for high analog-input frequencies. To achieve accurate results, it is critical to provide the ADC with a low-jitter, sampling clock source.

Architectural trade-offs
ADCs can be implemented by employing a variety of architectures. The principal trade-offs among these alternatives are:

* The time it takes to complete a conversion (conversion time). For flash converters, the conversion time does not change materially with increased resolution. The conversion time for successive approximation register (SAR) or pipelined converters, however, increases approximately linearly with an increase in resolution (Figure 3a). For integrating ADCs, the conversion time doubles with every bit increase in resolution.

* Component matching requirements in the circuit. Flash ADC component matching typically limits resolution to around 8 bits. Calibration and trimming are sometimes used to improve the matching available on chip. Component matching requirements double with every bit increase in resolution. This pattern applies to flash, successive approximation, or pipelined converters, but not to integrating converters. For integrating converters, component matching does not materially increase with an increase in resolution (Figure 3b).

* Die size, cost, and power. For flash converters, every bit increase in resolution almost doubles the size of the ADC core circuitry. The power also doubles. In contrast, a SAR, pipelined, or sigma-delta ADC die size will increase linearly with an increase in resolution; an integrating converter core die size will not materially change with an increase in resolution (Figure 3c). Finally, it is well known that an increase in die size increases cost.


Figure 3. Architectural trade-offs.

Flash ADC vs. other ADC architectures
Flash vs. SAR ADCs
In a SAR converter, a single high-speed, high-accuracy comparator determines the bits, one bit at a time (from the MSB down to the LSB). This is done by comparing the analog input with a DAC whose output is updated by previously decided bits and thus successively approximates the analog input. This serial nature of the SAR limits its speed to no more than a few mega-samples per second (Msps), while flash ADCs exceed giga-samples per second (Gsps) conversion rates.

SAR converters are available in resolutions up to 16 bits. An example of such a device is the MAX1132. Flash ADCs are typically limited to around 8 bits. The slower speed also allows the SAR ADC to be much lower in power. For example, the MAX1106, an 8-bit SAR converter, uses 100µA at 3.3V with a conversion rate of 25ksps. The MAX104 dissipates 5.25W, about 16,000 times higher power consumption than the MAX1106 and 40,000 times faster in terms of its maximum sampling rate.

The SAR architecture is also less expensive. The MAX1106 at 1k volumes sells at something over a dollar (U.S.), while the MAX104 sells at several hundred dollars (U.S.). Package sizes are larger for flash converters. In addition to a larger die size requiring a larger package, the package needs to dissipate considerable power and needs many pins for power and ground signal integrity. The package size of the MAX104 is more than 50 times larger than the MAX1106.

Flash vs. pipelined ADCs
A pipelined ADC employs a parallel structure in which each stage works on one to a few bits of successive samples concurrently. This design improves speed at the expense of power and latency, but each pipelined stage is much slower than a flash section. The pipelined ADC requires accurate amplification in the DACs and interstage amplifiers, and these stages have to settle to the desired linearity level. By contrast, in a flash ADC the comparator only needs to be low offset and to resolve its inputs to a digital level; there is no linear settling time involved. Some flash converters require preamplifers to drive the comparators. Gain linearity needs to be specified carefully.

Pipelined converters convert at speeds of around 100Msps at 8- to 14-bit resolutions. An example of a pipelined converter is the MAX1449, a 105MHz, 10-bit ADC. For a given resolution, pipelined ADCs are around 10 times slower than flash converters of similar resolution. Pipelined converters are possibly the optimal architecture for ADCs that need to sample at rates up to around 100Msps with resolution at 10 bits and above. For resolutions up to 10 bits and conversion rates above a few hundred Msps, flash ADCs dominate.

Interestingly, there are some situations where flash ADCs are hidden inside a converter employing another architecture to increase its speed. This is the case, for example, in the MAX1200; a 16-bit pipelined ADC that includes an internal 5-bit flash ADC.

Flash vs. integrating ADCs
Single, dual, and multislope ADCs achieve high resolutions of 16 bits or more, are relatively inexpensive, and dissipate materially less power. These devices support very low conversion rates, typically less than a few hundred samples per second. Most applications are for monitoring DC signals in the instrumentation and industrial markets. This architecture competes with sigma-delta converters.

Flash vs. sigma-delta ADCs
Flash ADCs do not compete with a sigma-delta architecture because currently the achievable conversion rates differ by up to two orders of magnitude. The sigma-delta architecture is suitable for applications with much lower bandwidth, typically less than 1MHz, and with resolutions in the 12- to 24-bit range. Sigma-delta converters are capable of the highest resolution possible in ADCs. They require simpler anti-alias filters (if needed) to bandlimit the signal prior to conversion.

Sigma-delta ADCs trade speed for resolution by oversampling, followed by filtering to reduce noise. However, these devices are not always efficient for multichannel applications. This architecture can be implemented by using sampled data filters, also known as modulators, or continuous-time filters. For higher frequency conversion rates the continuous-time architecture is potentially capable of reaching conversion rates in the hundreds of Msps range with low resolution of 6 to 8 bits. This approach is still in the early research and development stage and offers competition to flash alternatives in the lower conversion rate range.

Another interesting use of a flash ADC is as a building block inside a sigma-delta circuit to increase the conversion rate of the ADC.

Subranging ADCs
When higher resolution converters or smaller die size and power for a given resolution are needed, multistage conversion is employed. This architecture is known as a subranging converter, also sometimes referred to as a multistep or half-flash converter. This approach combines ideas from successive approximation and flash architectures.

Subranging ADCs reduce the number of bits to be converted into smaller groups, which are then run through a lower-resolution flash converter. This approach reduces the number of comparators and reduces the logic complexity compared to a flash converter (Figure 4). The trade-off results in a slower conversion speed compared to flash.


Figure 4. Subranging ADC architecture.

The MAX153 is an 8-bit, 1Msps ADC implemented with a subranging architecture. This circuit employs a two-step technique. First, a conversion is completed with a 4-bit converter. A residue is created, where an 8-bit accurate DAC converts the result of the 4-bit conversion back to an analog signal. The analog signal is subtracted from the input signal. Second, this residue is again converted by the 4-bit ADC and the results of the first and second pass are combined to provide the 8-bit digital output.

Process technology
Flash converter speeds are currently in excess of 1Gsps. The 2.2Gbps MAX109 is fabricated with an advanced SiGE process. The MAX108 (1.5Gsps), MAX104 (1Gsps), and MAX106 (600Msps) 8-bit ADCs are manufactured with Maxim's proprietary, advanced GST-2 bipolar process ("giga"-speed silicon bipolar process).

CMOS flash converters are available at lower speed with resolutions compared to bipolar technology offerings. These ADCs are typically intended for integration into a larger CMOS circuit. CMOS, BiCMOS, and bipolar technologies will continue to improve, yielding increasingly higher conversion rates.

Conclusion
For applications requiring modest resolutions, typically up to 8-bits, at sampling frequencies in the high hundreds of MHz, the flash architecture may be the only viable alternative. The user must supply a low-jitter clock to ensure good ADC performance. For applications with high analog-input frequencies, the ADC chosen should have an internal track-and-hold.

 Отправлено: 17.10.10 16:34. Заголовок: http://www.atmel.com..

 Отправлено: 17.10.10 16:49. Заголовок: dlja parralelnix ADC..

dlja parralelnix ADC yze w 2006 ispolzowalas texnologija 0.09 microna

http://cmoset.com/uploads/4.2-08.pdf<\/u><\/a> str.12

rastet potr .moschnost na kazdij rzrjad w 2 raza

8 bit -256 komparatorow
9 bit -512
10 bit -1024

 Отправлено: 17.10.10 17:02. Заголовок: ADS5400 TI 12 bit 1 ..

ADS5400 TI 12 bit 1 gsps stoit 775 $

samaja dorogaja verisja naibolee skorostnogo 16 bit/250 msps AD9467 stoit -300$

http://analogdevices.wordpress.com/2010/09/29/analog-devices-announces-industry%e2%80%99s-fastest-16-bit-adc-at-250-msps/<\/u><\/a>

http://www.analog.com/static/imported-files/data_sheets/AD9467.pdf<\/u><\/a>

APPLICATIONS
Multicarrier, multimode cellular receivers
Antenna array positioning
Power amplifier linearization
Broadband wireless
Radar
Infrared imaging
Communications instrumentation

Packaged in a Pb-free, 72-lead LFCSP package.
Total Power Dissipation (Including Output Drivers) 1.32 watt

SNR Fin 300 mgz 73.3/74.4 db
SINAD 300 mgz 73/74.1 db
ENOB 300 mgz 11.8/12 db
SFDR 300 mgz 92/90 db

250 msps ,maximum polosa 125 mgz

T.e. pri IF/Pch = 300 mgz AD9467 mozet skanirowat spektr 120 mgz ot 240 do 360 mgz
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Clock Jitter Considerations
High speed, high resolution ADCs are sensitive to the quality of the
clock input. The degradation in SNR at a given input frequency
(fA) due only to aperture jitter (tJ) can be calculated by
SNR = 20 × log 10(2 × π × fA × tJ)
In this equation, the rms aperture jitter represents the root mean
square of all jitter sources, including the clock input, analog input
signal, and ADC aperture jitter specifications. IF undersampling
applications are particularly sensitive to jitter (see Figure 17).

 Отправлено: 17.10.10 17:13. Заголовок: Mozno realizowat na ..

Mozno realizowat na imejsucheesja w Rossii nalichii staroj 0.13 micron ( 0.09 toze werojatno est i 0.065 ozidaetjsa
0.065 eto vektornij processor na odnom chipe -100 gigaflop ot NEC SX-9 ,resultat oktjabrja 2007 goda)

http://www.cmoset.com/uploads/8.4.pdf<\/u><\/a>

str.30

11 bit , 1 gigasample/sek

SNR 400 mgz 57.6 db
power -0.25 watt
ploschad -3.5 mm w^2


Applications landscape of time-interleaved ADC’s
studied
– Conventional architecture 1 usable for lower speed, higher
accuracy
– Conventional architecture 2 more optimal for higher speed,
lower accuracy.
– Proposed architecture (ISSCC 2006) covered a broader
landscape of ADC’s providing at
• Higher speeds: higher accuracy,
• Lower speeds:
– same accuracy at low power
– higher accuracy at similar power

 Отправлено: 17.10.10 17:17. Заголовок: Grazdanskoe primenen..

Grazdanskoe primenenie -blizajschee wremja sotowie seti w bolschisntwe ostanutsja WCDMA

http://www.analog.com/static/imported-files/application_notes/58327589985769549305955624592AN_807_0.pdf<\/u><\/a>


Multicarrier WCDMA Feasibility
by Brad Brannon and Bill Schofield



The key requirement of this wideband filtering is that signal aliasing is prevented. Therefore, any analog filtering must provide sufficient rejection so as to attenuate blockers into the noise floor as they alias back into the useable spectrum of the ADC. This is true for either IF sampling or direct conversion.


Assumptions: Given this information, the front-end design information can now be determined. If the largest peak signal at the antenna is about –36 dBm and the converter full scale is 4 dBm rms/7 dBm peak (2 V p-p into 200  is typical for many ADCs), a conversion gain of up to 43 dB can be used. A gain of 40 causes the ADC to be driven with a peak input of about +4 dBm, leaving 3 dB at the top that can serve as margin for power from other nearby strong signals as well as component margin. Given current receiver trends in LNAs, passive mixers and filter elements, typical downconverter blocks are possible with noise figures below 3 dB (not including the ADC). These numbers are used in the following calculations. If losses from cabling and other hardware are to be considered along with variations in component tolerance, they must be included as well.
The final assumption is that of sample rate for the ADC. With a base data rate of 3.84 MHz, clock rates of 16, 20, 24, and 32 are viable. Since converter data rates are steadily increasing and running, a higher sample rate has slight noise advantages. One of the higher rates, such as 92.16 MHz, should be used. If the lower rates are used for actual implementation, the SNR requirement increases by 1 dB for 76.8 MSPS and 2 dB for 61.44 MSPS. In addition to noise advantage, the higher sample rate allows more transition for band filters, as already discussed. If complex baseband sampling is used, a dual 12-bit or 14-bit converter family, such as the AD9228 and AD9248, are ideal.
ADC SNR requirements: Given the conversion gain and NF above, the ADC SNR can now be calculated. At the antenna, the noise spectral density is assumed to be –174 dBm/Hz. Given the conversion gain and noise figure previously stated, the noise spectral density (NSD) at the ADC input is –131 dBm/Hz (–174 + 40 + 3). This assumes that noise outside the Nyquist band of the ADC is filtered using antialiasing filters to prevent front-end thermal noise from aliasing when sampled by the ADC. If the ADC noise floor is 10 dB below that of the front-end noise, it contributes about 0.1 dB to the overall NF of the receiver. Therefore, a maximum ADC noise floor of –141 dBm/Hz can be expected. Higher ADC noise floors can be used. As the ADC noise begins to contribute to the floor of the receiver, some of the nonlinearities described in the “DNL and Some of its Effects on Converter Performance”


For IF sampling, the total noise in the Nyquist band of the ADC can be determined by simple integration. Over 46.08 MHz (the Nyquist band of 92.16 MHz), the total noise is found to be –64.4 dBm. If the rms full scale of the ADC is +4 dBm, this is a required minimum full-scale SNR of 68.4 dB. When larger blockers are considered, as in the case of band II and III, higher noise perform- ance is required from the ADC as seen in the following sections.
Although direct downconversion is not quite ready for this market space, it is the preferred architecture for cost and simplicity reasons. It is likely that this approach will be available within the scope of a new multicarrier development and is therefore considered in this application note.

 Отправлено: 17.10.10 17:23. Заголовок: For direct conversio..

For direct conversion, there are several other considerations that must be made. First, a lower sample rate is likely. Since two converters are required, it is likely that a lower sample rate is used to keep digital processing and power as low as possible. A sample rate of 61.44 MSPS is likely, providing a full 61.44 MHz of complex bandwidth. If it is assumed that the ADCs keep the same input range, a 3 dB increase is allowable since the IQ splitter also divides the power between the two ADCs in addition to the losses associated with a typical frequency translation stage. Without this additional gain, 3 dB (approximately) of ADC range will be lost. In the digital processing, these signals are again summed and produce an overall signal 3 dB higher along with a 3 dB higher ADC noise floor from the noncorrelated ADC noise floor of both ADCs. At the same time, however, the effective ADC input range is also 3 dB higher as is the noise floor of the effective ADC contributions. This results in a first-order wash in sensitivity as signal levels and noise each increase by the same amount. If the signal path includes the extra 3 dB gain, the IP3 requirements increase a proportionate amount. First order, each single ADC must also meet the same requirements for IF sampling. Although the sample rate is lower than may have otherwise been used for IF sampling, the noise bandwidth is equal to the full sample rate. The result is that the noise performance is similar to that of an IF sampling solution operating at 122.88 MSPS with two added advantages. First, because the analog signals are at baseband, clock jitter is no longer a problem. Second, because the analog signals are at baseband, they are not subjected to input slew rate limitations of the converter, which is one of the biggest causes of poor harmonic distortion in IF sampling systems.
The primary focus thus far has been to provide a fixed gain solution that meets the dynamic range requirements. This requires a delicate balance between placing the ADC noise sufficiently below the receiver analog thermal noise without overdriving the ADC. As discussed earlier, a converter with a minimum SNR of 68.4 dB makes this possible.


For baseband sampling, the AD9238 and AD9248 dual, 12-bit and 14-bit converters are available. These devices are pin compatible and allow assembly options for platforms that may be common between single and multicarrier applications and where export/import restrictions may exist. In addition to these pin-compatible devices, new quad ADCs are available, including the AD9228 and AD9229. These quad, 12-bit converters are ideal for diversity baseband IQ sampling or for quad, low IF sampling applications such as phased array antennas.

 Отправлено: 17.10.10 17:27. Заголовок: There are a number o..

There are a number of approaches to capture the distortion. One approach mixes the transmitted signal down close to dc and uses a high speed ADC to sample a bandwidth that is equal to the order of distortion times the bandwidth of the RF spectrum. A Nyquist band of 75 MHz and 100 MHz is required for three and four carriers respectively. Common sample rates of between 170 MHz and 210 MHz are used for this function (see Figure 15a).
An alternate approach mixes down to a low intermediate frequency (IF) and undersamples the transmitted signal. With this approach, the ADC samples the signal and the third-order distortion components without aliasing; the fifth- and higher order distortion terms are allowed to alias over the third-order terms and compensated by coefficient control (see Figure 15b). For four carriers at 153.6 MHz, a 122.88 MSPS converter is needed.
The ADC limitation is that it must introduce less distortion than the distortion being measured at the antenna and have a noise spectral density less than the antenna wideband emission requirements. The ADC noise can be averaged over multiple samples, relaxing the noise requirements of the ADC by the oversample ratio to typically 8 ENOB to 10 ENOB. The following discussion reveals a required noise level at 10 MHz offset is –30 dBm/1 MHz or –90 dBm/Hz. This level must be attenuated by typically 50 dB to reduce the maximum PA output to that of the ADC full scale; the directional coupler typically has about 40 dB of attenuation. Therefore, the spectral density at the ADC input is –140 dBm/Hz; across a 100 MHz Nyquist band, this corresponds to an ADC SNR of about 60 dB. The AD9430 provides mid 70s SFDR up to 200 MHz and an SNR of mid 60s, meeting these requirements.

 Отправлено: 17.10.10 17:54. Заголовок: ATMEL’s TS8388 ADC J..

ATMEL’s TS8388 ADC Jitter
• According to ATMEL’s TS8388 ADC data-sheet (1GS/s,
8-bit & ENOB=7.1-bit), cited by Bill Jones, JAPJ=0.6 ps
JCLK=0.5 ps.
• Assuming JAIN=0.5 ps then JADC=0.93 ps
• From formula ENOB=7.4-bit
• High-speed ADC ENOB’s are jitter limited
#####################################
• GS/s, ENOB > 6.5-bit ADCs are hard to integrate on a
VLSI CMOS chip due to excess recovered clock’s jitter
#####################################
• Recovered clock period:
1200 ps (PAM-10), 800 ps (PAM-5)

http://www.ieee802.org/3/10GBT/public/mar03/babanezhad_2_0303.pdf<\/u><\/a>

 Отправлено: 17.10.10 18:10. Заголовок: http://solidearth.jp..

 Отправлено: 17.10.10 18:23. Заголовок: High-Resolution Mode..

High-Resolution Mode: The High-Resolution Mode is an 80 MHz mode that trades
swath coverage for increased resolution (10 m). One of seven beams may be chosen
in this mode; each with a swath width of ~40 km. Operation in this mode would be in lieu
of the primary 35 m resolution Stripmap Mode and would be performed intermittently at
the request of the Science Team when targets of interest requiring higher resolution are
identified

The current InSAR baseline eight-day sun-synchronous orbit at 760 km altitude yields a
separation of ~340 km at the equator between adjacent nadir tracks, as shown in the
following figure. In order to meet the requirement for complete global access the InSAR
Payload System will be designed such that the accessible area (viewable swath) is
greater than or equal to 340 km.

 Отправлено: 17.10.10 19:15. Заголовок: http://www.fujitsu.c..

 Отправлено: 17.10.10 20:33. Заголовок: http://i.cmpnet.com/..