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Сообщение: 1860
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Отправлено: 13.11.09 15:19. Заголовок: Operazionnie ysiliteli ,ZAP/AZP & (продолжение)
1941: First (vacuum tube) op-amp An op-amp, defined as a general-purpose, DC-coupled, high gain, inverting feedback amplifier, is first found in US Patent 2,401,779 "Summing Amplifier" filed by Karl D. Swartzel Jr. of Bell labs in 1941. This design used three vacuum tubes to achieve a gain of 90dB and operated on voltage rails of ±350V. ###################################################### It had a single inverting input rather than differential inverting and non-inverting inputs, as are common in today's op-amps. Throughout World War II, Swartzel's design proved its value by being liberally used in the M9 artillery director designed at Bell Labs. ######################################################################### This artillery director worked with the SCR584 radar system to achieve extraordinary hit rates (near 90%) that ####################################################################### would not have been possible otherwise.[3] ########################### http://en.wikipedia.org/wiki/Operational_amplifier
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Отправлено: 17.10.10 17:23. Заголовок: For direct conversio..
For direct conversion, there are several other considerations that must be made. First, a lower sample rate is likely. Since two converters are required, it is likely that a lower sample rate is used to keep digital processing and power as low as possible. A sample rate of 61.44 MSPS is likely, providing a full 61.44 MHz of complex bandwidth. If it is assumed that the ADCs keep the same input range, a 3 dB increase is allowable since the IQ splitter also divides the power between the two ADCs in addition to the losses associated with a typical frequency translation stage. Without this additional gain, 3 dB (approximately) of ADC range will be lost. In the digital processing, these signals are again summed and produce an overall signal 3 dB higher along with a 3 dB higher ADC noise floor from the noncorrelated ADC noise floor of both ADCs. At the same time, however, the effective ADC input range is also 3 dB higher as is the noise floor of the effective ADC contributions. This results in a first-order wash in sensitivity as signal levels and noise each increase by the same amount. If the signal path includes the extra 3 dB gain, the IP3 requirements increase a proportionate amount. First order, each single ADC must also meet the same requirements for IF sampling. Although the sample rate is lower than may have otherwise been used for IF sampling, the noise bandwidth is equal to the full sample rate. The result is that the noise performance is similar to that of an IF sampling solution operating at 122.88 MSPS with two added advantages. First, because the analog signals are at baseband, clock jitter is no longer a problem. Second, because the analog signals are at baseband, they are not subjected to input slew rate limitations of the converter, which is one of the biggest causes of poor harmonic distortion in IF sampling systems. The primary focus thus far has been to provide a fixed gain solution that meets the dynamic range requirements. This requires a delicate balance between placing the ADC noise sufficiently below the receiver analog thermal noise without overdriving the ADC. As discussed earlier, a converter with a minimum SNR of 68.4 dB makes this possible. For baseband sampling, the AD9238 and AD9248 dual, 12-bit and 14-bit converters are available. These devices are pin compatible and allow assembly options for platforms that may be common between single and multicarrier applications and where export/import restrictions may exist. In addition to these pin-compatible devices, new quad ADCs are available, including the AD9228 and AD9229. These quad, 12-bit converters are ideal for diversity baseband IQ sampling or for quad, low IF sampling applications such as phased array antennas.
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milstar
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Сообщение: 4806
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Отправлено: 17.10.10 17:27. Заголовок: There are a number o..
There are a number of approaches to capture the distortion. One approach mixes the transmitted signal down close to dc and uses a high speed ADC to sample a bandwidth that is equal to the order of distortion times the bandwidth of the RF spectrum. A Nyquist band of 75 MHz and 100 MHz is required for three and four carriers respectively. Common sample rates of between 170 MHz and 210 MHz are used for this function (see Figure 15a). An alternate approach mixes down to a low intermediate frequency (IF) and undersamples the transmitted signal. With this approach, the ADC samples the signal and the third-order distortion components without aliasing; the fifth- and higher order distortion terms are allowed to alias over the third-order terms and compensated by coefficient control (see Figure 15b). For four carriers at 153.6 MHz, a 122.88 MSPS converter is needed. The ADC limitation is that it must introduce less distortion than the distortion being measured at the antenna and have a noise spectral density less than the antenna wideband emission requirements. The ADC noise can be averaged over multiple samples, relaxing the noise requirements of the ADC by the oversample ratio to typically 8 ENOB to 10 ENOB. The following discussion reveals a required noise level at 10 MHz offset is –30 dBm/1 MHz or –90 dBm/Hz. This level must be attenuated by typically 50 dB to reduce the maximum PA output to that of the ADC full scale; the directional coupler typically has about 40 dB of attenuation. Therefore, the spectral density at the ADC input is –140 dBm/Hz; across a 100 MHz Nyquist band, this corresponds to an ADC SNR of about 60 dB. The AD9430 provides mid 70s SFDR up to 200 MHz and an SNR of mid 60s, meeting these requirements.
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milstar
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Отправлено: 17.10.10 17:54. Заголовок: ATMEL’s TS8388 ADC J..
ATMEL’s TS8388 ADC Jitter • According to ATMEL’s TS8388 ADC data-sheet (1GS/s, 8-bit & ENOB=7.1-bit), cited by Bill Jones, JAPJ=0.6 ps JCLK=0.5 ps. • Assuming JAIN=0.5 ps then JADC=0.93 ps • From formula ENOB=7.4-bit • High-speed ADC ENOB’s are jitter limited ##################################### • GS/s, ENOB > 6.5-bit ADCs are hard to integrate on a VLSI CMOS chip due to excess recovered clock’s jitter ##################################### • Recovered clock period: 1200 ps (PAM-10), 800 ps (PAM-5) http://www.ieee802.org/3/10GBT/public/mar03/babanezhad_2_0303.pdf<\/u><\/a>
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Сообщение: 4809
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Отправлено: 17.10.10 18:23. Заголовок: High-Resolution Mode..
High-Resolution Mode: The High-Resolution Mode is an 80 MHz mode that trades swath coverage for increased resolution (10 m). One of seven beams may be chosen in this mode; each with a swath width of ~40 km. Operation in this mode would be in lieu of the primary 35 m resolution Stripmap Mode and would be performed intermittently at the request of the Science Team when targets of interest requiring higher resolution are identified The current InSAR baseline eight-day sun-synchronous orbit at 760 km altitude yields a separation of ~340 km at the equator between adjacent nadir tracks, as shown in the following figure. In order to meet the requirement for complete global access the InSAR Payload System will be designed such that the accessible area (viewable swath) is greater than or equal to 340 km.
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