In fact, this is a very conservative scenario. The PRF is rather low and the number of antenna array inputs is very small. Should the number of antenna array inputs increase by 12 to 48, the processing load of the matrix processing, in particular QR Decomposition, goes up by the third power or 64 times. This would require over 3 TeraFLOPs of realtime floating point processing power. Because of this, the limitations on STAP are clearly the processing capabilities of the radar system.
The theory of STAP has been known for a long time, but the processing requirements have made it impractical until fairly recently. Many radar applications benefiting from STAP are airborne and often have stringent size, weight, and power (SWaP) constraints. Very few processing architectures can meet the throughput requirements of STAP, while even fewer can simultaneously meet the SWaP constraints.
his approach is known as “Fused Datapath”, and when combined with Altera’s new 28nm Variable Precision DSP block architecture, offers extremely high data processing capabilities, in excess of one Teraflop on a single FPGA die.
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